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SL74HC595 Datasheet(PDF) 5 Page - System Logic Semiconductor

Part No. SL74HC595
Description  8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
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Maker  SLS [System Logic Semiconductor]
Homepage  http://www.slsemicon.co.kr/e_index.htm
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SL74HC595 Datasheet(HTML) 5 Page - System Logic Semiconductor

 
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SL74HC595
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to
-55
°C
≤85
°C
≤125
°C
Unit
fmax
Minimum Clock Frequency (50% Duty Cycle)
(Figures 1and 7)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH, tPHL
Maximum Propagation Delay, Shift Clock to SQH
(Figures 1and 7)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
tPHL
Maximum Propagation Delay , Reset to SQH
(Figures 2 and 7)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
tPLH, tPHL
Maximum Propagation Delay , Latch Clock to QA-
QH (Figures 3 and 7)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
tPLZ, tPHZ
Maximum Propagation Delay , Output Enable to
QA-QH (Figures 4 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZL, tPZH
Maximum Propagation Delay , Output Enable to
QA-QH (Figures 4 and 8)
2.0
4.5
6.0
135
27
23
170
34
29
205
41
35
ns
tTLH, tTHL
Maximum Output Transition Time, QA-QH (Figures
3 and 7)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tTLH, tTHL
Maximum Output Transition Time, SQH
(Figures 1 and 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
COUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State), QA-QH
-
15
15
15
pF
Power Dissipation Capacitance (Per Package)
Typical @25
°C,V
CC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC
2f+I
CCVCC
300
pF


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