74ACT11620

OCTAL BUS TRANSCEIVER

WITH 3STATE OUTPUTS

SCAS060A − D2957, JULY 1987 − REVISED APRIL 1993

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Copyright

1

PCB Layout

Minimize High-Speed Switching Noise

CMOS) 1-

mm Process

125

°C

Outline Packages, and Standard Plastic

300-mil DIPs

description

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The

control function implementation allows for maximum flexibility in timing.

These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending

upon the logic levels at the enable inputs (GBA and GAB).

The enable inputs can be used to disable the device so that the buses are effectively isolated.

The dual-enable configuration gives these devices the capability to store data by simultaneous eanbling of GBA

and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are

enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16

in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will be complementary

for the 74ACT11620.

The 74ACT11620 is characterized for operation from − 40

°C to 85°C.

GBA

L

H

H

GAB

L

H

L

B data to A bus

A data to B bus

Isolation

B data to A bus,

A data to B bus

OPERATION

ENABLE INPUTS

LH

FUNCTION TABLE

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

A1

A2

A3

A4

GND

GND

GND

GND

A5

A6

A7

A8

GAB

B1

B2

B3

B4

B5

B6

B7

B8

GBA

DW OR NT PACKAGE

(TOP VIEW)

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.