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74ACT11273DW Datasheet(PDF) 1 Page - Texas Instruments |
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74ACT11273DW Datasheet(HTML) 1 Page - Texas Instruments |
1 / 11 page 74ACT11273 OCTAL DTYPE FLIPFLOP WITH CLEAR SCAS130 − D3443, MARCH 1990 − REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 Copyright 1993, Texas Instruments Incorporated 2−1 • Inputs Are TTL-Voltage Compatible • Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators • Flow-Through Architecture Optimizes PCB Layout • Multiple Center-Pin V CC and GND Configurations Minimize High-Speed Switching Noise • EPICt (Enhanced-Performance Implanted CMOS) 1- mm Process • 500-mA Typical Latch-Up Immunity at 125 °C • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description These positive-edge-triggered flip-flops implement D-type flip-flop logic with a direct clear input. Data at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The 74ACT11273 is characterized for operation from − 40 °C to 85°C. FUNCTION TABLE INPUTS OUTPUT CLR CLOCK D OUTPUT Q L X X L H ↑ HH H ↑ LL H L X Q0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q CLR 1D 2D 3D 4D VCC VCC 5D 6D 7D 8D CLK DW OR NT PACKAGE (TOP VIEW) 1D CLK 2D 3D 4D 24 13 23 22 21 20 1D G1 C1 5D 6D 17 16 1Q 2Q 3Q 4Q 1 2 3 4 5Q 6Q 9 10 7D 8D 15 14 7Q 8Q 11 12 CLR logic symbol† † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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