ADS7843

9

SBAS090B

www.ti.com

1

DCLK

CS

81

11

DOUT

BUSY

S

DIN

CONTROL BITS

S

CONTROL BITS

10

98765

4

3210

11 10

9

81

1

8

next 12th clock cycles accomplish the actual A/D conversion.

switches are on during the conversion. A 13th clock cycle is

needed for the last bit of the conversion result. Three more

clock cycles are needed to complete the last byte (DOUT will

be LOW). These will be ignored by the converter.

Control Byte

See Figure 5 for the placement and order of the control bits

within the control byte. Tables III and IV give detailed informa-

tion about these bits. The first bit, the ‘S’ bit, must always be

HIGH and indicates the start of the control byte. The ADS7843

will ignore inputs on the DIN pin until the start bit is detected.

The next three bits (A2-A0) select the active input channel or

channels of the input multiplexer (see Tables I and II and

Figure 2). The MODE bit determines the number of bits for

each conversion, either 12 bits (LOW) or 8 bits (HIGH).

ended (HIGH) or differential (LOW). (The differential mode is

also referred to as the ratiometric conversion mode.) In single-

ended mode, the converter’s reference voltage is always the

mode, the reference voltage is the difference between the

currently enabled switches. See Tables I and II and Figures 2

through 4 for more information. The last two bits (PD1-PD0)

select the power-down mode as shown in Table V. If both

inputs are HIGH, the device is always powered up. If both

inputs are LOW, the device enters a power-down mode

between conversions. When a new conversion is initiated, the

device will resume normal operation instantly—no delay is

needed to allow the device to power up and the very first

conversion will be valid. There are two power-down modes:

PD1

PD0

PENIRQ

DESCRIPTION

0

0

Enabled

Power-down between conversions. When each

conversion is finished, the converter enters a low

power mode. At the start of the next conversion,

the device instantly powers up to full power.

There is no need for additional delays to assure

full operation and the very first conversion is

valid. The Y– switch is on while in power-down.

0

1

Disabled

Same as mode 00, except PENIRQ is disabled.

The Y– switch is off while in power-down mode.

1

0

Disabled

Reserved for future use.

1

1

Disabled

No power-down between conversions, device is

always powered.

TABLE V. Power-Down Selection.

FIGURE 6. Conversion Timing, 16 Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated

Serial Port.

BIT

NAME

DESCRIPTION

7

S

Start Bit. Control byte starts with first HIGH bit on

DIN. A new control byte can start every 16th clock

cycle in 12-bit conversion mode or every 12th clock

cycle in 8-bit conversion mode.

6-4

A2-A0

Channel Select Bits. Along with the SER/DFR bit,

these bits control the setting of the multiplexer input,

switches, and reference inputs, see Tables I and II.

3

MODE

12-Bit/8-Bit Conversion Select Bit. This bit controls

the number of bits for the following conversion: 12

bits (LOW) or 8 bits (HIGH).

2

SER/DFR

Single-Ended/Differential Reference Select Bit. Along

with bits A2-A0, this bit controls the setting of the

multiplexer input, switches, and reference inputs, see

Tables I and II.

1-0

PD1-PD0

Power-Down Mode Select Bits. See Table V for

details.

TABLE IV. Descriptions of the Control Bits within the Control

Byte.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(MSB)

(LSB)

S

A2

A1

A0

MODE SER/DFR

PD1

PD0

TABLE III. Order of the Control Bits in the Control Byte.

16-Clocks per Conversion

The control bits for conversion n + 1 can be overlapped with

conversion ‘n’ to allow for a conversion every 16 clock cycles,

as shown in Figure 6. This figure also shows possible serial

communication occurring with other serial peripherals between

each byte transfer between the processor and the converter.