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CY62147EV30 Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY62147EV30 Datasheet(HTML) 6 Page - Cypress Semiconductor |
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6 / 18 page  CY62147EV30 MoBL® Document Number: 38-05440 Rev. *M Page 6 of 18 Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ [11] Max Unit VDR VCC for data retention 1.5 – – V ICCDR [12] Data retention current VCC = 1.5 V, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V –0.8 7 A tCDR [13] Chip deselect to data retention time 0–– ns tR [14] Operation recovery time 45 – – ns Data Retention Waveform Figure 5. Data Retention Waveform [15, 16] VCC(min) VCC(min) tCDR VDR > 1.5V DATA RETENTION MODE tR VCC CE or BHE.BLE Notes 11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 12. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 13. Tested initially and after any design or process changes that may affect these parameters. 14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 15. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 16. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE. |
Similar Part No. - CY62147EV30_12 |
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Similar Description - CY62147EV30_12 |
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