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CYWB0224ABSX-FDXI Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CYWB0224ABSX-FDXI
Description  West Bridge짰: Astoria??USB and Mass Storage Peripheral Controller
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYWB0224ABSX-FDXI Datasheet(HTML) 5 Page - Cypress Semiconductor

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CYWB022XX Family
Document Number: 001-13805 Rev. *M
Page 5 of 78
GPIF and GPIO Interface
The GPIF and GPIO interface mode configure the S-Port to
support GPIF and GPIO as shown in Figure 5. Each GPIO is
configured as either input or output independently. The
processor accesses those GPIO through the P-Port driver’s API.
Figure 5. GPIF and GPIO Interface Mode
GPIO Interface Mode
The GPIO interface mode configures the S-Port to all GPIO as
shown in Figure 6. Each GPIO is configured as either input or
output independently. The processor accesses those GPIO
through the P-Port driver’s API.
Figure 6. GPIO Interface Mode
SD/SDIO/MMC+/CE-ATA Port (S-Port)
When Astoria is configured with firmware to support SD, SDIO,
MMC+, and CE-ATA, this interface supports:
The Multimedia Card System Specification, MMCA Technical
Committee, Version 4.1
SD Memory Card Specification – Part 1, Physical Layer
Specification, SD Group, Version 1.10, October 15, 2004
SD Memory Card Specification – Part 1, Physical Layer
Specification, SD Group, Version 2.0, May 9, 2006
SD Specifications – Part E1 SDIO Specification, Version 1.10,
August 18, 2004
CE-ATA Specification – CE-ATA Digital Protocol, CE-ATA
Committee, Version 1.1, September, 2005
West Bridge Astoria provides support for 1-bit and 4-bit SD;
SDIO cards; 1-bit, 4-bit, and 8-bit MMC; MMC+ cards; and
CE-ATA drive. For the SD, SDIO, MMC/MMC Plus, and CE-ATA,
this block supports one card for one physical bus interface.
Astoria supports SD commands including the multisector
program command that are handled by the API.
GPIO Port (S-Port)
The GPIO in S-Port is configurable as either input or output
direction independently. The processor accesses the GPIO
through the P-Port driver’s API.
Clocking
Astoria allows connection of a crystal between the XTALIN and
XTALOUT pins or an external clock at the XTALIN pin. The
81-ball WLCSP package only supports the external clock. The
power supply level at the crystal supply XVDDQ determines
whether a crystal or a clock is provided. If XVDDQ is detected to
be 1.8 V, Astoria assumes that a clock input is provided. For a
crystal to be connected, XVDDQ must be 3.3 V.
Note Clock inputs at 3.3 V level are not supported.
Astoria’s 100-ball VFBGA package supports external crystal and
clock inputs at 19.2, 24, and 26 MHz frequencies. At 48 MHz,
only clock inputs are supported. The 81-ball SPWLCSP only
supports 19.2 and 26 MHz external clock input. The 81-ball Lite
SP WLCSP only supports 26 MHz external clock or crystal input.
The crystal or clock frequency selection is shown in Table 1 on
page 6, Table 2 on page 6, and Table 3 on page 6.
The XTALIN frequency is independent of the clock and data rate
of the 8051 microprocessor or any of the device interfaces
(including P-Port and S-Port). The internal PLL applies the
proper clock multiply option depending on the input frequency.
For applications that use an external clock source to drive
XTALIN, the XTALOUT pin must be left floating. The external
clock source must also stop high or low and not toggle, to
achieve the lowest possible current consumption. The
requirements for an external clock source are shown in Table 4
on page 6.
Astoria has an on-chip oscillator circuit that uses an external
19.2, 24, and 26 MHz (±150 ppm) crystal with the following
characteristics:
Parallel resonant
Fundamental mode
1 mW drive level
12 pF (5% tolerance) load capacitors
150 ppm
GPIO
Astoria
S Port


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