CY2308

Document Number: 38-07146 Rev. *M

Page 8 of 18

Switching Characteristics for Industrial Temperature Devices

Parameter [13]

Name

Test Conditions

Min Typ

Max

Unit

Input frequency

–

10

–

133.3

MHz

Output frequency

30 pF load

10

–

100 (-1,-2,-3,-4)

66.67 (-5H)

MHz

Output frequency

20 pF load, -1H, -5H devices

10

–

133.3 (-1H)

66.67 (-5H)

MHz

Output frequency

15 pF load, -1, -2, -3, -4 devices

10

–

133.3

MHz

(-1, -2, -3, -4, -1H, -5H)

load

40.0 50.0

60.0

%

(-1, -2, -3, -4, -1H, -5H)

55.0

%

Rise time [13, 14] (-1, -2, -3, -4)

Measured between 0.8 V and 2.0 V, 30 pF load

–

–

2.50

ns

Rise time [13, 14] (-1, -2, -3, -4)

Measured between 0.8 V and 2.0 V, 15 pF load

–

–

1.50

ns

Rise time [13, 14] (-1H, -5H)

Measured between 0.8 V and 2.0 V, 30 pF load

–

–

1.50

ns

Fall time [13, 14] (-1, -2, -3, -4)

Measured between 0.8 V and 2.0 V, 30 pF load

–

–

2.50

ns

Fall time [13, 14] (-1, -2, -3, -4)

Measured between 0.8 V and 2.0 V, 15 pF load

–

–

1.50

ns

Fall time [13, 14] (-1H, -5H)

Measured between 0.8 V and 2.0 V, 30 pF load

–

–

1.25

ns

Output to output skew on same

Bank [13, 14] (-1, -2, -3, -4)

All outputs equally loaded

–

–

200

ps

Output to output skew (-1H, -5H) All outputs equally loaded

–

–

200

ps

Output Bank A to output Bank B

skew (-1, -4, -5H)

All outputs equally loaded

–

–

200

ps

Output Bank A to output Bank B

skew (-2, -3)

All outputs equally loaded

–

–

400

ps

Delay, REF rising edge to FBK

rising edge [13, 14]

–

0

250

ps

Device to device skew [13, 14]

–

0

700

ps

Output slew rate [13, 14]

Measured between 0.8 V and 2.0 V on -1H, -5H

device using Test Circuit 2

1–

–

V/ns

Cycle to cycle Jitter [13, 14] (-1,

-1H, -4, -5H)

Measured at 66.67 MHz, loaded outputs, 15 pF

load

–

75

200

ps

Measured at 66.67 MHz, loaded outputs, 30 pF

load

–

–

200

ps

Measured at 133.3 MHz, loaded outputs, 15 pF

load

–

–

100

ps

Cycle to cycle Jitter [13, 14] (-2,

-3)

Measured at 66.67 MHz, loaded outputs, 30 pF

load

–

–

400

ps

Measured at 66.67 MHz, loaded outputs, 15 pF

load

–

–

400

ps

PLL lock time [13, 14]

Stable power supply, valid clocks presented on

REF and FBK pins

––

1.0

ms

Notes

13. All parameters are specified with loaded outputs.

14. Parameter is guaranteed by design and characterization. Not 100% tested in production.

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