CYWB0224ABS-BZXI datasheet(9/78 Pages) CYPRESS

Part #	CYWB0224ABS-BZXI

Description	West Bridge짰: Astoria??USB and Mass Storage Peripheral Controller

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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9 / 78 page

CYWB022XX Family

Document Number: 001-13805 Rev. *M

Page 9 of 78

Pin Assignments

Table 6. Astoria 100-ball VFBGA Package Pin Assignments

Pin Name

Pin Description

Power

Domain

Ball #

PCRAM

Non-Multiplexing

I/O

Address / Data

bus Multiplexing

(ADM)

I/O

SRAM

I/O

PNAND

I/O

SPI

I/O

J2

CLK (pull low in

Asyn mode)

I CLK (pull low in

Async mode)

I Ext pull low

I SCK

I

Clock

PVDDQ

VGND

G1

CE#I CE#I CE#I CE#I SS#

I

CE# or SPI Slave

Select

H3

A7

I Ext pull up

I A7

I A7 > 1:SBD

A7 > 0:LBD

I Ext pull up

I

Addr. Bus 7

H2

A6

I SDA

I A6

I SDA

I/O SDA

I/O A6 or I2C data

H1

A5

I SCL

I A5

I SCL

I/O SCL

I/O A5 or I2C clock

J3

A4

I Ext pull up

I A4

I WP#

I Ext pull up

I

A4 or PNAND WP

J1

A3

I A3 = 0 (Ext pull

low)

I A3

I A3 = 0 (Ext pull

low)

I A3 = 1 (Ext pull up)

I

A3

K3

A2

I A2 = 1 (Ext pull up) I A2

I A2 = 0 (Ext pull

low)

I A2 = 0 (Ext pull

low)

IA2

K2

A1

I Ext pull up

I A1

I RB#

O Ext pull up

I

A1 or PNAND R/B#

K1

A0

I Ext pull up

I A0

I CLE

I Ext pull up

I

A0 or PNAND CLE

G2

DQ[15]

I/O AD[15]

I/O DQ[15]

I/O I/O[15]

I/O Ext pull up

I

D15, AD15, or I/O15

G3

DQ[14]

I/O AD[14]

I/O DQ[14]

I/O I/O[14]

I/O Ext pull up

I

D14, AD14, or I/O14

F1

DQ[13]

I/O AD[13]

I/O DQ[13]

I/O I/O[13]

I/O Ext pull up

I

D13, AD13, or I/O13

F2

DQ[12]

I/O AD[12]

I/O DQ[12]

I/O I/O[12]

I/O Ext pull up

I

D12, AD12, or I/O12

F3

DQ[11]

I/O AD[11]

I/O DQ[11]

I/O I/O[11]

I/O Ext pull up

I

D11, AD11, or I/O11

E1

DQ[10]

I/O AD[10]

I/O DQ[10]

I/O I/O[10]

I/O Ext pull up

I

D10, AD10, or I/O10

E2

DQ[9]

I/O AD[9]

I/O DQ[9]

I/O I/O[9]

I/O Ext pull up

I

D9, AD9, or I/O9

E3

DQ[8]

I/O AD[8]

I/O DQ[8]

I/O I/O[8]

I/O Ext pull up

I

D8, AD8, or I/O8

D1

DQ[7]

I/O AD[7]

I/O DQ[7]

I/O I/O[7]

I/O Ext pull up

I

D7, AD7, or I/O7

D2

DQ[6]

I/O AD[6]

I/O DQ[6]

I/O I/O[6]

I/O Ext pull up

I

D6, AD6, or I/O6

D3

DQ[5]

I/O AD[5]

I/O DQ[5]

I/O I/O[5]

I/O Ext pull up

I

D5, AD5, or I/O5

C1

DQ[4]

I/O AD[4]

I/O DQ[4]

I/O I/O[4]

I/O Ext pull up

I

D4, AD4, or I/O4

C2

DQ[3]

I/O AD[3]

I/O DQ[3]

I/O I/O[3]

I/O Ext pull up

I

D3, AD3, or I/O3

C3

DQ[2]

I/O AD[2]

I/O DQ[2]

I/O I/O[2]

I/O Ext pull up

I

D2, AD2, or I/O2

B1

DQ[1]

I/O AD[1]

I/O DQ[1]

I/O I/O[1]

I/O SDO

O

SPI SDO, AD1or D1

B2

DQ[0]

I/O AD[0]

I/O DQ[0]

I/O I/O[0]

I/O SDI

I

SPI SDI, AD0, or D0

A1

ADV#

I ADV#

I

I ALE

I Ext pull up

I

Address Valid

B3

OE#

I OE#

I RE#

I Ext pull up

I

Output Enable

A2

WE#

I WE#

I Ext pull up

I

WE#

A3

INT#

O INT#

O SINT#

O

INT Request

GVDDQ

VGND

A4

DRQ#

O DRQ#

O N/C

O

DMA Request

B4

DACK#

I DACK#

I Ext pull up

I

DMA

Acknowledgement

A5

D+

I/O/Z USB D+

UVDDQ

UVSSQ

A6

D–

I/O/Z USB D–

A7

SWD+

I/O/Z USB Switch DP

C6

SWD–

I/O/Z USB Switch DM

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