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CYWB0224ABM-BVXIES Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CYWB0224ABM-BVXIES Datasheet(HTML) 7 Page - Cypress Semiconductor |
7 / 78 page CYWB022XX Family Document Number: 001-13805 Rev. *M Page 7 of 78 Figure 8. Astoria Power Supply Domains Power Supply Sequence The power supplies are independently sequenced without damaging the part. All power supplies must be up and stable before the device operates. If the supplies are not stable, the remaining domains are in low power (standby) state. Power Modes In addition to the normal operating mode, Astoria contains several low power states when normal operation is not required. Normal Mode Normal mode is the mode in which Astoria is fully functional. In this mode, data transfer functions described in this document are performed. Suspend Mode This mode is entered internally by 8051 (the external processor only initiates entry into this mode through Mailbox commands). This mode is exited by the D+ bus going low, GPIO[0] going to a pre-determined state or by asserting CE# LOW. In Astoria’s suspend mode: ■ The clocks are shut off ■ All I/Os maintain their previous state ■ Core power supply must be retained ■ The states of the configuration registers, endpoint buffers, and the program RAM are maintained. All transactions must be complete before Astoria enters suspend mode (state of outstanding transactions are not preserved) ■ The firmware resumes its operation from where it was suspended because the program counter is not reset ■ Only inputs that are sensed are RESET#, GPIO[0]/SD_CD, GPIO[1]/SD2_CD, SD_D3, SD2_D3, D+, and CE#. The last three are wake up sources (each can be individually enabled or disabled) ■ Hard Reset can be performed by asserting the RESET# input, and Astoria is initialized Standby Mode Standby mode is a low-power state. This is the lowest power mode of Astoria while still maintaining external supply levels. This mode is entered through the deassertion of the WAKEUP input pin or through internal register settings. To leave this mode, assert the WAKEUP, CE#, and RESET#; change state of GPIO[0]/SD_CD, GPIO[1]/SD2_CD, SD_D3, and SD2_D3. In this mode all configuration register settings and program RAM contents are preserved. However, data in the buffers or other parts of the data path, if any, is not guaranteed in values. Therefore, the external processor must ensure that the required data is read before placing Astoria in the standby mode. In the standby mode: ■ The program counter is reset on waking up from standby mode ■ All outputs are tristated and I/O is placed in input only configuration. Values of I/Os in standby mode are listed in the pin assignments table ■ Core power supply must be retained ■ Hard Reset can be performed by asserting the RESET# input, and Astoria is initialized ■ PLL is disabled ■ USB switches the SWD+/SWD– to D+/D– Core Power Down Mode The core power supply VDD is powered down in this state. Because AVDDQ is tied to the same supply as VDD, it is also powered down. The endpoint buffers, configuration registers, and program RAM do not maintain state. All VDDQ power supplies (except AVDDQ) must be ON and not power down in this mode. VDD33 must also remain ON. It has an option that the UVDDQ can be powered down or stay ON while VDD is powered down when SWD+/SWD– are not connected. The UVDDQ cannot be powered down when SWD+/SWD– is connected, or VDD is active. When UVDDQ is powered down, D+/D– cannot be driven by an external device. In the WLCSP package, AVDDQ is internally tied to XVDDQ. Due to this, the clock input at XTALIN must be brought to a steady low level prior to entry into Core Power Down Mode. In the WLCSP package, VDD33 is tied to UVDDQ internally. UVDDQ must be ON during the core power down mode The core power down mode has two power down options: ■ Core only power down – VDD power down ■ Core and USB power down – VDD and UVDDQ are both powered down. In this option, SWD+/SWD– are not connected and cannot be driven by an external device In these power down options, the endpoint buffers, configuration registers, or the program RAM do not maintain state. It is necessary to reload the firmware on exiting from this mode. All VDDQ power supplies must be ON and not powered down in this mode. In the 82-ball WLCSP package, in the core power down mode, the USB switches the SWD+/SWD– to D+/D–. USB-IO D-CORE I/O UVDDQ VDD D+ D- *VDDQ |
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