CYF2018V18L-100BGXI datasheet(11/31 Pages) CYPRESS

Part #	CYF2018V18L-100BGXI

Description	18/36/72-Mbit Programmable Multi-Queue FIFOs

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CYF2018V

CYF2036V

CYF2072V

Document Number: 001-68336 Rev. *C

Page 11 of 31

Width Expansion Configuration

The width of CYF2072V can be expanded to provide word widths

greater than 36 bits. During width expansion mode, all control

line inputs are common and all flags are available. Empty (Full)

flags are created by ANDing the Empty (Full) flags of every FIFO.

This technique avoids reading data from or writing data to the

FIFO that is “staggered” by one clock cycle due to the variations

in skew between RCLK and WCLK. Figure 3 demonstrates an

example of a 72 bit-word width by using two 36-bit word

CYF2072Vs.

Memory Organization for Different Port Sizes

The 72-Mbit memory has different organization for different port

sizes. Table 6 shows the depth of the FIFO for all port sizes.

Note that for all port sizes, four to eight locations are not available

for writing the data and are used to safeguard against false

synchronization of empty and full flags.

The memory size mentioned is when the device is configured in

single-Queue mode.

Figure 2. Serial WRITE to Configuration Register

Figure 3. Using Two CYF2072Vs for Width Expansion

FF

EF

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

FF

CYF2072V

36

72

DATA IN (D)

36

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE(OE)

36

DATA OUT (Q)

36

72

EF

Table 6. Word Size Selection

PORTSZ[2:0]

Word Size

FIFO Depth

Memory Size

000

× 9

8 Meg

72 Mbit

001

× 12

4 Meg

48 Mbit

010

× 16

4 Meg

64 Mbit

011

× 18

4 Meg

72 Mbit

100

× 20

2 Meg

40 Mbit

101

× 24

2 Meg

48 Mbit

110

× 32

2 Meg

64 Mbit

111

× 36

2 Meg

72 Mbit

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CYF2018V18L-100BGXI Datasheet(PDF) 11 Page - Cypress Semiconductor

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