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CYF2018V18L-100BGXI Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CYF2018V18L-100BGXI Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 31 page  CYF2018V CYF2036V CYF2072V Document Number: 001-68336 Rev. *C Page 9 of 31 Write Mask and Read Skip Operation As mentioned in Architecture on page 7, enabling writes but disabling the inputs (IE HIGH) increments the write pointer without doing any write operations or altering the contents of the location. This feature is called Write Mask and allows user to move the write pointer without actually writing to the locations. This “write masking” ability is useful in some video applications such as Picture In Picture (PIP). Similarly, during a read operation, if the outputs are disabled by having the OE high, the read data does not appear on the output bus; however, the read pointer is incremented. Multi-Queue Operation In general, the entire memory space is accessed as a single Fist In First Out (FIFO) order for the write and read operation. In this case, the entire memory space is called a single Queue. For example, for 72M device, the entire memory space is available as a single FIFO memory. In multi Queue mode, the entire memory space is divided into equal sized memory array and each individual memory array can be accessed as an independent FIFO based on additional control signals. These independent memory arrays are called as Queues. For example, when 72M device, is configured into eight Queue mode, the entire memory space of 72M is divided into eight 9M memory array called as Queue-0 to Queue-7. These Queues can be accessed independently as a FIFO by selecting the Queue select signals WQSEL[2:0] and RQSEL[2:0]. In this way, upto eight Queues can be created for a given device where data can be stored independently and read out independently. It is possible to configure the whole memory space of CYF2072V into 8 or 4 or 2 equal sized array, and each array can be independently accessed as an independent FIFO. This is like having eight or four or two independent Queues inside the FIFO instead of entire memory space acting as single Queue FIFO. The number of Queues is configured based on the value of D2, D1 & D0 bit of configuration register 0x3 (refer to Table 3). Table 2 on page 8 shows the value to be set in D2, D1 & D0 of configuration register 0x3 to configure the device in 1/2/4/8 Queue modes. . Table 3. Configuration Registers ADDR Configuration Register Default Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0] 0x1 Reserved 0x00 XXX XXX XX 0x2 Reserved 0x00 XXX XXX XX 0x3 Number of Queues 0x00 Enable Queue registers X X X X D2 D1 D0 0x4 Reserved 0x7F XXX XXX XX 0x5 Reserved 0x00 XXX XXX XX 0x6 Reserved 0x00 XXX XXX XX 0x7 Reserved 0x7F XXX XXX XX 0x8 Reserved 0x00 XXX XXX XX 0x9 Reserved 0x00 XXX XXX XX 0xA Fast CLK Bit Register 1XXXXXXXb Fast CLK bit XX XXX XX Table 4. Writing and Reading Configuration Registers in Parallel Mode SPI_SEN LD WEN REN WCLK RCLK SPI_SCLK Operation 1 001 First rising edge because both LD and WEN are low X X Parallel write to first register 1 001 Second rising edge X X Parallel write to second register 1 001 Third rising edge X X Parallel write to third register 1 001 Fourth rising edge X X Parallel write to fourth register 1 001 XX 1 001 XX 1 001 XX 1 001 Tenth rising edge X X Parallel write to tenth register |
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