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CY62167EV30LL-45ZXI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY62167EV30LL-45ZXI Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 19 page  CY62167EV30 MoBL® 16-Mbit (1 M × 16 / 2 M × 8) Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-05446 Rev. *L Revised July 9, 2012 16-Mbit (1 M × 16 / 2 M × 8) Static RAM Features ■ TSOP I package configurable as 1 M × 16 or 2 M × 8 SRAM ■ Very high speed: 45 ns ■ Temperature ranges ❐ Industrial: –40 °C to +85 °C ❐ Automotive-A: –40 °C to +85 °C ■ Wide voltage range: 2.20 V to 3.60 V ■ Ultra-low standby power ❐ Typical standby current: 1.5 A ❐ Maximum standby current: 12 A ■ Ultra-low active power ❐ Typical active current: 2.2 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2, and OE Features ■ Automatic power-down when deselected ■ CMOS for optimum speed and power ■ Offered in Pb-free 48-ball VFBGA and 48-pin TSOP I packages Functional Description The CY62167EV30 is a high performance CMOS static RAM organized as 1M words by 16 bits or 2M words by 8 bits. This device features an advanced circuit design that provides an ultra low active current. Ultra low active current is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: the device is deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or a write operation is in progress (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from the I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See Truth Table on page 12 for a complete description of read and write modes. 1M × 16 / 2M x 8 RAM Array I/O0–I/O7 A 8 A 7 A 6 A 5 A 2 COLUMN DECODER DATA IN DRIVERS OE A 4 A 3 I/O8–I/O15 WE BLE BHE A 0 A 1 A 9 A10 CE2 CE1 BYTE Power Down Circuit BHE BLE CE2 CE1 Logic Block Diagram |
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