CY29946

Document #: 38-07286 Rev. *G

Page 2 of 9

CY29946

VSS

QB0

VDDC

QB1

VSS

QB2

VDDC

VDDC

TCLK_SEL

VDD

TCLK0

TCLK1

DSELA

DSELB

DSELC

VSS

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

Pin Configuration

Pin Description[1]

Pin

Name

PWR

I/O

Description

3, 4

TCLK(0,1)

I, PU External Reference/Test Clock Input

26, 28, 30

QA(2:0)

VDDC

O

Clock Outputs

19, 21, 23

QB(2:0)

VDDC

O

Clock Outputs

10, 12, 14, 16

QC(0:3)

VDDC

O

Clock Outputs

5, 6, 7

DSEL(A:C)

I, PD Divider Select Inputs. When HIGH, selects

2 input divider. When LOW,

selects

1 input divider.

1

TCLK_SEL

I, PD TCLK Select Input. When LOW, TCLK0 clock is selected and when HIGH

TCLK1 is selected.

32

MR/OE#

I, PD Output Enable Input. When asserted LOW, the outputs are enabled and

when asserted HIGH, internal flip-flops are reset and the outputs are

three-stated. If more than 1 Bank is being used in /2 Mode, a reset must be

performed (MR/OE# Asserted High) after power-up to ensure all internal

flip-flops are set to the same state.

9, 13, 17, 18, 22,

25, 29

VDDC

2.5 V or 3.3 V Power Supply for Output Clock Buffers

2

VDD

2.5 V or 3.3 V Power Supply

8, 11, 15, 20, 24,

27, 31

VSS

Common Ground

Note

1. PD = Internal pull-down. PU = Internal pull-up.

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