CY25560

Document #: 38-07425 Rev. *G

Page 3 of 13

Pinouts

Figure 1. Pin Configuration – 8-Pin SOIC Package

General Description

The Cypress CY25560 is a spread spectrum clock generator

(SSCG) IC used to reduce the EMI found in today’s high-speed

digital electronic systems.

The CY25560 uses Cypress’s proprietary phase-locked loop

(PLL) and spread spectrum clock (SSC) technology to

synthesize and frequency modulate the input frequency of the

reference clock. By frequency modulating the clock, the

measured EMI at the fundamental and harmonic frequencies of

clock (SSCLK) is greatly reduced.

This reduction in radiated energy can significantly reduce the

cost of complying with regulatory requirements and time to

market without degrading system performance.

The CY25560 is a very simple and versatile device to use. The

frequency and spread% range is selected by programming S0

and S1 digital inputs. These inputs use three (3) logic states

including High (H), Low (L), and Middle (M) logic levels to select

one of the nine available spread% ranges. See the Table 2 on

page 4 for programming details.

CY25560 is optimized for SVGA (40 MHz) and XVGA (65 MHz)

controller clocks and also suitable for applications where the

frequency range is 25 MHz to 100 MHz.

A wide range of digitally selectable spread percentages is made

possible by using three-level (High, Low, and Middle) logic at the

S0 and S1 digital control inputs.

The output spread (frequency modulation) is symmetrically

centered on the input frequency.

Spread spectrum clock control (SSCC) function enables or

disables the frequency spread and is provided for easy

comparison of system performance during EMI testing.

The CY25560 is available in an 8-pin SOIC package with 0

C to

70

C Commercial and –40 C to 85 C Industrial operating

temperature ranges.

Table 1. Pin Description

Pin Number Pin Name

Type

Pin Description

1

Xin/CLK

I

Clock or crystal connection input. See the Table 2 on page 4 for input frequency range selection.

2

VDD

P

Positive power supply.

3

GND

P

Power supply ground.

4

SSCLK

O

Modulated clock output, that is the same frequency as the input clock or the crystal frequency.

5

SSCC

I

Spread spectrum clock control (enable/disable) function. SSCG function is enabled when input

is high and disabled when input is low. This pin is pulled high internally.

6

S1

I

Tri-level logic input control pin used to select input frequency range and spread percent. See

the “Tri-Level Logic” on page 4 for programming details. Pin 6 has an internal resistor divider

7

S0

I

Tri-level logic input control pin used to select input frequency range and spread percent. See

the “Tri-Level Logic” on page 4 for programming details. Pin 7 has an internal resistor divider

8

Xout

O

Oscillator output pin connected to crystal. Leave this pin unconnected if an external clock is

used to drive xin/clk input (Pin 1).

1

2

3

4

8

7

6

5

XIN/CLK

VDD

VSS

XOUT

S0

S1

SSCC

CY25560

SSCLK