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CY22801KFXCT Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY22801KFXCT
Description  Universal Programmable Clock Generator (UPCG)
Download  25 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY22801KFXCT Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY22801
Document Number: 001-15571 Rev. *H
Page 5 of 25
Multifunction Pins
There are three pins [1] with multiple functions either as control
pins or as output pins. The following are the acronyms used for
the different control function pins:
Output enable (OE): If OE = 1, all outputs are enabled
Frequency select (FS0, 1, 2): These pins can be used to select
one of the programmed clock frequencies for clock output. All
of three multifunction pins support this functionality. Any of
these pins can also be configured as Spread spectrum ON
(SSON) pin. If SSON = 1, clock output has programmed
spread; if SSON = 0, clock output does not have spread.
Power-down: active low (PD#): If PD# = 0, all outputs are
tristated and the device enters in the low-power state
Voltage controlled crystal oscillator (VCXO): Analog voltage on
this pin controls the output frequency of oscillator
Serial interface clock line (SCLK) and serial interface data line
(SDAT): These pins are for serial interface and are compatible
with I2C.
Each of these three multi-function pins supports selected
functions mentioned in Table 1. One of the supported functions
can be programmed on the pin at a time.
Frequency Calculation and Register
Definitions
The CY22801 is an extremely flexible clock generator with four
basic variables that are used to determine the final output
frequency. They are the input reference frequency (REF), the
internally calculated P and Q dividers, and the post divider, which
can be a fixed or calculated value. There are three formulas to
determine the final output frequency of a CY22801 based
design:
CLK = ((REF × P) / Q) / Post divider
CLK = REF / Post divider
CLK = REF
The basic PLL block diagram is shown in Figure 4. Each of the
three clock outputs on the CY22801 has a total of seven output
options available to it. There are six post divider options
available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N
and DIV2N are independently calculated and are applied to
individual output groups. The post divider options can be applied
to the calculated VCO frequency ((REF × P) / Q) or to the REF
directly.
In addition to the six post divider output options, the seventh
option bypasses the PLL and passes the REF directly to the
crosspoint switch matrix.
Table 1. Multi Function Pin Options
Pin#
Pin Name
OE
PD# VCXO FS
CLK
OUTPUT
I2C
3
SDAT / FS0 /
VCXO / OE /
PD#
YY
Y[2]
Y[3]
N[4]
SDAT[2]
5
CLKB / FS1 /
SCLK
NN
N
Y
Y
SCLK
7CLKC / FS2
N
N
N
Y
Y[5]
N
Table 2. Possible Combinations for Multifunction Pins
Possible Combinations
Pin#3
Pin#5
Pin#7
A
FS0
CLKB
CLKC
B
FS0
CLKB
FS2
C
FS0
FS1
FS2
D
OE / PD#
CLKB
CLKC
E
OE / PD#
FS1
CLKC
F
OE / PD#
FS1
FS2
G
SDAT
SCLK
CLKC
H
VCXO
CLKB
CLKC
Notes
1. There are Weak Pull up resistors (approximately 100 k
) on all Multifunctional pins.
2. VCXO and SSON functions as well as VCXO and Serial Interface functions are not compatible.
3. ‘Y’ means pin supports this function.
4. ‘N’ means pin does not support this function.
5. Do not use this pin as Reference Clock Output.


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