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CY23FS08OXIT Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY23FS08OXIT Datasheet(HTML) 4 Page - Cypress Semiconductor |
4 / 15 page CY23FS08 Document Number: 38-07518 Rev. *F Page 4 of 15 FailSafe Function The CY23FS08 is targeted at clock distribution applications that requires or may require continued operation if the main reference clock fails. Existing approaches to this requirement have used multiple reference clocks with either internal or external methods to switch between references. The problem with this technique is that it leads to interruptions (or glitches) when transitioning from one reference to another, often requiring complex external circuitry or software to maintain system stability. The technique implemented in this design completely eliminates any switching of references to the PLL, greatly simplifying system design. The CY23FS08 PLL is driven by the crystal oscillator, which is phase-aligned to an external reference clock so that the output of the device is effectively phase-aligned to reference via the external feedback loop. This is accomplished by using a digitally controlled capacitor array to pull the crystal frequency over an approximate range of ±300 ppm from its nominal frequency. In this mode, if the reference frequency fails (that is, stops or disappears), the DCXO maintains its last setting and a flag signal (FAIL#/SAFE) is set to indicate failure of the reference clock. The CY23FS08 provides four select bits, S1 through S4 to control the reference to crystal frequency ratio. The DCXO is internally tuned to the phase and frequency of the external reference only when the reference frequency divided by this ratio is within the DCXO capture range. If the frequency is out of range, a flag is set on the FAIL#/SAFE pin notifying the system that the selected reference is not valid. If the reference moves in range, then the flag is cleared, indicating to the system that the selected reference is valid. Figure 2. Fail#/Safe Timing for Input Reference Failing Catastrophically 0101 8.50 30 6.80 24.00 1.70 6.00 44/5 1/5 1011 8.33 30 25.00 90.00 6.25 22.50 43 3/4 0011 8.33 30 2.78 10.00 2.78 10.00 ×1 1/3 1/3 1001 8.33 30 8.33 30.00 8.33 30.00 ×1 1 1 1111 8.00 25 32.00 100.00 32.00 100.00 ×1 4 4 1100 8.00 25 64.00 200.00 64.00 200.00 ×1 8 8 0001 8.33 30 1.04 3.75 2.08 7.50 ×2 1/8 1/4 0110 8.33 30 4.17 15.00 8.33 30.00 ×2 1/2 1 1101 8.33 30 16.67 60.00 33.33 120.00 ×2 2 4 0100 8.33 30 4.17 15.00 16.67 60.00 ×4 1/2 2 1010 8.33 30 12.50 45.00 50.00 180.00 ×4 3/2 6 0010 8.33 30 1.39 5.00 11.11 40.00 ×8 1/6 4/3 0111 8.33 30 6.25 22.50 50.00 180.00 ×8 3/4 6 Table 2. Configuration Table (continued) S[4:1] XTAL (MHz) REF(MHz) OUT(MHz) REF:OUT Ratio REF:XTAL Ratio Out:XTAL Ratio Min Max Min Max Min Max RE F OU T F A I L#/ S A F E t FS L t FS H [+] Feedback |
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