CY23FP12

200 MHz Field Programmable Zero

Delay Buffer

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document #: 38-07246 Rev. *G

Revised January 18, 2011

Features

Functional Description

The CY23FP12 is a high performance fully field-programmable

200 MHz zero delay buffer designed for high speed clock distri-

bution. The integrated PLL is designed for low jitter and

optimized for noise rejection. These parameters are critical for

reference clock distribution in systems using high performance

ASICs and microprocessors.

The CY23FP12 is fully programmable through volume or

prototype programmers, enabling the user to define an appli-

cation-specific Zero Delay Buffer with customized input and

output dividers, feedback topology (internal/external), output

inversions, and output drive strengths. For additional flexibility,

the user can mix and match multiple functions listed in Table 2,

and assign a particular function set to any one of the four

possible S1-S2 control bit combinations. This feature enables

the implementation of four distinct personalities, selectable with

S1-S2 bits, on a single programmed silicon. The CY23FP12 also

features a proprietary auto power down circuit that shuts down

the device in case of a REF failure, resulting in less than 50

μA

of current draw.

The CY23FP12 provides 12 outputs grouped in two banks with

separate power supply pins which can be connected indepen-

dently to either a 2.5 V or a 3.3 V rail.

Selectable reference input is a fault tolerance feature which

enables glitch-free switch over to a secondary clock source when

REFSEL is asserted/deasserted.

FBK

÷M

÷N

100 to

400MHz

PLL

CLKA1

CLKA3

CLKA2

REF2

REFSEL

CLKA4

CLKA5

CLKB1

CLKB3

CLKB2

CLKB4

CLKB5

VDDA

VSSA

VDDB

VSSB

÷2

÷3

÷4

÷X

CLKA0

VDDC

VSSC

÷1

Lock Detect

Test Logic

REF1

CLKB0

S[2:1]

Function

Selection

Logic Block Diagram

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