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CY23S02 Datasheet(PDF) 2 Page - Cypress Semiconductor

Part # CY23S02
Description  Spread Aware?? Frequency Multiplier, and Zero Delay Buffer
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY23S02 Datasheet(HTML) 2 Page - Cypress Semiconductor

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CY23S02
Document #: 38-07155 Rev. *E
Page 2 of 10
Overview
The CY23S02 is a two-output zero delay buffer and frequency
multiplier. It provides an external feedback path allowing
maximum flexibility when implementing the Zero Delay feature.
This is explained further in the sections of this data sheet titled
“How to Implement Zero Delay,” and “Inserting Other Devices in
Feedback Path.”
The CY23S02 is a pin-compatible upgrade of the Cypress
W42C70-01. The CY23S02 addresses some application
dependent problems experienced by users of the older device.
Most importantly, it addresses the tracking skew problem
induced by a reference that has Spread Spectrum Timing
enabled on it.
Spread Aware
Many systems being designed now utilize a technology called
spread spectrum frequency timing generation. Cypress has
been one of the pioneers of SSFTG development, and we
designed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a zero
delay buffer is not designed to pass the SS feature through, the
result is a significant amount of tracking skew which may cause
problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology, please
see the Cypress application note titled, “EMI Suppression
Techniques with Spread Spectrum Frequency Timing Generator
(SSFTG) ICs.”
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
IN
2
I
Reference Input: The output signals will be synchronized to this signal.
FBIN
1
I
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback
is equal in length to the traces between the outputs and the signal destinations, then the
signals received at the destinations will be synchronized to the REF signal input (IN).
OUT1
6
O
Output 1: The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see Table 1).
OUT2
8
O
Output 2: The frequency of the signal provided by this pin is one-half of the frequency
of OUT1. See Table 1.
VDD
7P
Power Connections: Connect to 3.3V or 5V. This pin should be bypassed with a 0.1-
F
decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter perfor-
mance.
GND
3
P
Ground Connection: Connect all grounds to the common system ground plane.
FS0:1
4, 5
I
Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per
Table 1.


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