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CY14B104LA-BA45XI Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY14B104LA-BA45XI
Description  4-Mbit (512 K 횞 8/256 K 횞 16) nvSRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14B104LA-BA45XI Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY14B104LA, CY14B104NA
Document Number: 001-49918 Rev. *L
Page 7 of 26
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power-down cycles.
The part comes from the factory with AutoStore enabled and
0x00 written in all cells.
Data Protection
The CY14B104LA/CY14B104NA protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected
when
VCC
<
VSWITCH.
If
the
CY14B104LA/CY14B104NA is in a write mode (both CE and WE
are LOW) at power-up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after tLZHSB (HSB to output
active). This protects against inadvertent writes during power-up
or brown out conditions.
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Output data
Output data
Output data
Output data
Output data
Output data
Active[14]
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
STORE
Output data
Output data
Output data
Output data
Output data
Output high Z
Active ICC2[14]
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
RECALL
Output data
Output data
Output data
Output data
Output data
Output high Z
Active[14]
Table 1. Mode Selection (continued)
CE
WE
OE
BHE, BLE[11]
A15–A0[12]
Mode
I/O
Power
Note
14. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.


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