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CY14B256Q1A-SXIT Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY14B256Q1A-SXIT Datasheet(HTML) 7 Page - Cypress Semiconductor |
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7 / 32 page  CY14C256Q CY14B256Q CY14E256Q Document Number: 001-65282 Rev. *E Page 7 of 32 9 for details. Invalid Opcode If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI pin till the next falling edge of CS and the SO pin remains tristated. Status Register CY14X256Q has an 8-bit Status Register. The bits in the Status Register are used to configure the SPI bus. These bits are described in the Table 4 on page 10. SPI Modes CY14X256Q may be driven by a microcontroller with its SPI peripheral running in either of the following two modes: ■ SPI Mode 0 (CPOL = 0, CPHA = 0) ■ SPI Mode 3 (CPOL = 1, CPHA = 1) For both these modes, the input data is latched in on the rising edge of SCK starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles, is considered. The output data is available on the falling edge of SCK. The two SPI modes are shown in Figure 5 and Figure 6. The status of clock when the bus master is in standby mode and not transferring data is: ■ SCK remains at 0 for Mode 0 ■ SCK remains at 1 for Mode 3 CPOL and CPHA bits must be set in the SPI controller for either Mode 0 or Mode 3. The device detects the SPI mode from the status of SCK pin when the device is selected by bringing the CS pin LOW. If SCK pin is LOW when the device is selected, SPI Mode 0 is assumed and if SCK pin is HIGH, it works in SPI Mode 3. Figure 4. System Configuration Using SPI nvSRAM uC o n trolle r SC K MO S I MIS O SI SO O S I S K C SS C K CS HO L D HO L D CS CS 1 CS 2 HO L D 1 HO L D 2 CY14X256Q CY14X256Q Figure 5. SPI Mode 0 Figure 6. SPI Mode 3 LSB MSB 7 654 32 10 CS SCK SI 0 1 2 3 4 5 6 7 CS SCK SI 7 654 32 10 LSB MSB 0 1 2 3 4 5 6 7 |
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