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CY8C24423A-24LTXIT Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY8C24423A-24LTXIT Datasheet(HTML) 3 Page - Cypress Semiconductor |
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3 / 65 page  CY8C24123A CY8C24223A CY8C24423A Document Number: 38-12028 Rev. *R Page 3 of 65 PSoC Functional Overview The PSoC family consists of many programmable system-on-chips with on-chip controller devices. These devices are designed to replace multiple traditional MCU-based system components with a low-cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture makes it possible for you to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The PSoC architecture, shown in Figure 1, consists of four main areas: PSoC core, digital system, analog system, and system resources. Configurable global busing allows combining all the device resources into a complete custom system. The PSoC CY8C24x23A family can have up to three I/O ports that connect to the global digital and analog interconnects, providing access to four digital blocks and six analog blocks. PSoC Core The PSoC core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIOs. The M8C CPU core is a powerful processor with speeds up to 24 Hz, providing a four-MIPS 8-bit Harvard-architecture microprocessor. The CPU uses an interrupt controller with 11 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included sleep and watchdog timers (WDT). Memory encompasses 4 KB of flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the flash. Program flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz internal low speed oscillator (ILO) is provided for the sleep timer and WDT. If crystal accuracy is required, the ECO (32.768 kHz external crystal oscillator) is available for use as a real time clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin can generate a system interrupt on high level, low level, and change from last read. Digital System The digital system consists of four digital PSoC blocks. Each block is an 8-bit resource that may be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user module references. Figure 1. Digital System Block Diagram Digital peripheral configurations are: ■ PWMs (8- and 16-bit) ■ PWMs with dead band (8- and 16-bit) ■ Counters (8- to 32-bit) ■ Timers (8- to 32-bit) ■ UART 8-bit with selectable parity ■ SPI master and slave ■ I2C slave and multi-master (one is available as a system resource) ■ CRC generator (8- to 32-bit) ■ IrDA ■ PRS generators (8- to 32-bit) The digital blocks may be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This gives a choice of system resources for your application. Family resources are shown in Table 1 on page 5. DIGITAL SYSTEM To System Bus Digital Clocks From Core Digital PSoC Block Array To Analog System 8 8 8 8 Row 0 DBB00 DBB01 DCB02 DCB03 4 4 GIE[7:0] GIO[7:0] GOE[7:0] GOO[7:0] Global Digital Interconnect Port 2 Port 1 Port 0 |
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