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CY8C24423A-24SXIT Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY8C24423A-24SXIT Datasheet(HTML) 11 Page - Cypress Semiconductor |
11 / 65 page CY8C24123A CY8C24223A CY8C24423A Document Number: 38-12028 Rev. *R Page 11 of 65 32-Pin Part Pinout Notes 6. The center pad on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 7. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details. Table 5. 32-Pin QFN[6] Pin No. Type Pin Name Description Figure 6. CY8C24423A 32-Pin PSoC Device Digital Analog 1 I/O P2[7] 2 I/O P2[5] 3 I/O I P2[3] Direct switched capacitor block input 4 I/O I P2[1] Direct switched capacitor block input 5 Power VSS Ground connection 6 Power SMP SMP connection to external components required 7 I/O P1[7] I2C SCL 8 I/O P1[5] I2C SDA 9 NC No connection. Pin must be left floating 10 I/O P1[3] 11 I/O P1[1] XTALin, I2C SCL, ISSP-SCLK[7] 12 Power VSS Ground Connection 13 I/O P1[0] XTALout, I2C SDA, ISSP-SDATA[7] 14 I/O P1[2] 15 I/O P1[4] Optional EXTCLK 16 NC No connection. Pin must be left floating 17 I/O P1[6] 18 Input XRES Active high external reset with internal pull-down 19 I/O I P2[0] Direct switched capacitor block input 20 I/O I P2[2] Direct switched capacitor block input 21 I/O P2[4] External AGND 22 I/O P2[6] External VREF 23 I/O I P0[0] Analog column mux input 24 I/O I P0[2] Analog column mux input 25 NC No connection. Pin must be left floating 26 I/O I P0[4] Analog column mux input 27 I/O I P0[6] Analog column mux input 28 Power VDD Supply voltage 29 I/O I P0[7] Analog column mux input 30 I/O I/O P0[5] Analog column mux input and column output 31 I/O I/O P0[3] Analog column mux input and column output 32 I/O I P0[1] Analog column mux input LEGEND: A = Analog, I = Input, and O = Output. P2[7] P2[5] A, I, P2[3] A, I, P2[1] VSS SMP QFN (Top View) 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 I2C SCL, P1[7] I2C SDA, P1[5] P0[2], A, I P0[0], A, I XRES P1[6] P2[6], External VRef P2[4], External AGND P2[2], A, I P2[0], A, I |
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