CY8C20336H, CY8C20446H

Document Number: 001-56223 Rev. *D

Page 10 of 35

48-Pin QFN OCD

The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit

debugging.[9]

Table 3. Pin Definitions - CY8C20066A PSoC Device [10, 11]

Pin

No.

Name

Description

Figure 4. CY8C20066A PSoC Device

1

OCDOE

OCD mode direction pin

2

I/O

I

P2[7]

3

I/O

I

P2[5]

Crystal output (XOut)

4

I/O

I

P2[3]

Crystal input (XIn)

5

I/O

I

P2[1]

6

I/O

I

P4[3]

7

I/O

IP4[1]

8

I/O

I

P3[7]

9

I/O

I

P3[5]

10

I/O

I

P3[3]

11

I/O

I

P3[1]

12

IOHR

I

P1[7]

13

IOHR

I

P1[5]

14

CCLK

OCD CPU clock output

15

HCLK

OCD high speed clock output

16

IOHR

I

P1[3]

SPI CLK.

17

IOHR

I

P1[1]

18

Power

Vss

Ground connection

19

I/O

D+

USB D+

20

I/O

D-

USB D-

21

Power

Supply voltage

22

IOHR

I

P1[0]

23

IOHR

I

P1[2]

Pin

No.

Name

Description

24

IOHR

I

P1[4]

Optional external clock input

(EXTCLK)

37

IOH

I

P0[0]

25

IOHR

I

P1[6]

38

IOH

I

P0[2]

26

Input

XRES

Active high external reset with

internal pull down

39

IOH

I

P0[4]

27

I/O

I

P3[0]

40

IOH

I

P0[6]

28

I/O

IP3[2]

41

Power

Supply voltage

29

I/O

IP3[4]

42

OCDO

OCD even data I/O

30

I/O

IP3[6]

43

OCDE

OCD odd data output

31

I/O

I

P4[0]

44

IOH

I

P0[7]

32

I/O

I

P4[2]

45

IOH

I

P0[5]

33

I/O

I

P2[0]

46

IOH

I

P0[3]

Integrating input

34

I/O

I

P2[2]

47

Power

Ground connection

35

I/O

I

P2[4]

48

IOH

I

P0[1]

36

I/O

I

P2[6]

CP

Power

Center pad must be connected to ground

LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.

Notes

9. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.

11. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it

must be electrically floated and not connected to any other signal.

12. These are the ISSP pins, which are not High Z at power on reset (POR).

QFN

(Top View)

10

11

12

AI, P2[7]

AI, XOut, P2[5]

AI, XIn , P2[3]

AI , P2[1]

AI , P4[3]

AI , P4[1]

AI , P3[7]

AI , P3[5]

AI , P3[3]

AI , P3[1]

AI, I2 C SCL, SPI SS, P1[7]

35

34

33

32

31

30

29

28

27

26

25

36

P2[4] ,AI

P2[2] ,AI

P2[0] ,AI

P4[2] ,AI

P4[0] ,AI

P3[6] ,AI

P3[4] , AI

P3[2] ,AI

P3[0] , AI

XRES

P1[6] , AI

P2[6] ,AI

1

2

3

4

5

6

7

8

9

OCDOE