CY7C09269V/79V/89V

CY7C09369V/89V

Document Number: 38-06056 Rev. *I

Page 5 of 22

Selection Guide

Specifications

CY7C09269V/79V/89V

CY7C09369V/89V

-7[10]

CY7C09269V/79V/89V

CY7C09369V/89V

-9

CY7C09269V/79V/89V

CY7C09369V/89V

-12

83

67

50

Max. Access Time (ns) (Clock to Data, Pipelined)

7.5

9

12

155

135

115

Level)

25

20

20

Level)

10

10

10

Pin Definitions

Left Port

Right Port

Description

Address Strobe Input. Used as an address qualifier. This signal must be asserted LOW to access

the part using an externally supplied address. Asserting this signal LOW also loads the burst counter

with the address present on the address pins.

Counter Enable Input. Asserting this signal LOW increments the burst address counter of its

respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW.

Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective

port to zero. CNTRST is not disabled by asserting ADS or CNTEN.

Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower

OE signals must be asserted to drive output data on the lower byte of the data pins.

Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read

operations.

Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For

read operations, assert this pin HIGH.

Flow Through/Pipelined Select Input. For flow through mode operation, assert this pin LOW. For

pipelined mode operation, assert this pin HIGH.

GND

Ground Input.

NC

No Connect.

Power Input.

Note

10. See Figure 4 on page 8 for Load Conditions.