CY7C15632KV18-500BZXI datasheet(10/30 Pages) CYPRESS

Part #	CY7C15632KV18-500BZXI

Description	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C15632KV18

Document Number: 001-54932 Rev. *F

Page 10 of 30

Write Cycle Descriptions

The write cycle description table for CY7C15632KV18 follows. [11, 12]

BWS0/

NWS0

BWS1/

NWS1

K

Comments

L

L–H

–

During the data portion of a write sequence



CY7C15632KV18

both bytes (D[17:0]) are written into the device.

L

–

L–H During the data portion of a write sequence:

CY7C15632KV18

both bytes (D[17:0]) are written into the device.

L

H

L–H

–

During the data portion of a write sequence:

CY7C15632KV18

only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.

L

H

–

L–H During the data portion of a write sequence



CY7C15632KV18

only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.

H

L

L–H

–

During the data portion of a write sequence



CY7C15632KV18

only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.

H

L

–

L–H During the data portion of a write sequence



CY7C15632KV18

only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.

H

L–H

–

No data is written into the devices during this portion of a write operation.

H

–

L–H No data is written into the devices during this portion of a write operation.

Notes

11. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,

represents rising edge.

12. Is based on a write cycle that was initiated in accordance with Write Cycle Descriptions. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different

portions of a write cycle, as long as the setup and hold requirements are achieved.

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