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SL4052B Datasheet(PDF) 3 Page - System Logic Semiconductor |
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SL4052B Datasheet(HTML) 3 Page - System Logic Semiconductor |
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3 / 6 page  SL4052B System Logic Semiconductor SLS DC ELECTRICAL CHARACTERISTICS Digital Section VCC Guaranteed Limit Symbol Parameter Test Conditions V ≥ -55 °C ≤ 25 °C ≤ 125 °C Unit VIH Minimum High-Level Input Voltage, Channel- Select or Enable Inputs VIS=VCC thru 1k Ω VEE=GND IIS<2 µA on all OFF Chanels RL=1k Ω to GND 5 10 15 3.5 7 11 3.5 7 11 3.5 7 12 V VIL Maximum Low -Level Input Voltage, Channel- Select or Enable Inputs VIS=VCC thru 1k Ω VEE=GND IIS<2 µA on all OFF Chanels RL=1k Ω to GND 5 10 15 1.5 3 4 1.5 3 4 1.4 3 4 V IIN Maximum Input Leakage Current, Channel-Select or Enable Inputs VIN=VCC or GND 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) Channel Select = VCC or GND 5 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 µA DC ELECTRICAL CHARACTERISTICS Analog Section VCC Guaranteed Limit Symbol Parameter Test Conditions V ≥ -55 °C ≤ 25 °C ≤ 125 °C Unit RON Maximum “ON” Resistance VEE=GND=0 VIS = GND to VCC 5 10 15 800 310 200 1050 400 240 1300 550 320 Ω ∆R ON Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package VEE=GND=0 5 10 15 - - - 10 15 5 - - - Ω IOFF Maximum Off- Channel Leakage Current, Any One Channel VEE=GND=0 18 ±100 ±100 ±1000 nA Maximum Off- Channel Leakage Current, Common Channel VEE=GND=0 18 ±100 ±100 ±1000 |
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