CY7C1525KV18

CY7C1512KV18

CY7C1514KV18

Document Number: 001-00436 Rev. *P

Page 8 of 34

Functional Overview

The CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18

are synchronous pipelined Burst SRAMs with a read port and a

write port. The read port is dedicated to read operations and the

write port is dedicated to write operations. Data flows into the

SRAM through the write port and flows out through the read port.

These devices multiplex the address inputs to minimize the

number of address pins required. By having separate read and

write ports, the QDR II completely eliminates the need to turn

around the data bus and avoids any possible data contention,

thereby simplifying system design. Each access consists of two

9-bit data transfers in the case of CY7C1525KV18, two 18-bit

data transfers in the case of CY7C1512KV18, and two 36-bit

data transfers in the case of CY7C1514KV18 in one clock cycle.

This device operates with a read latency of one and half cycles

when DOFF pin is tied HIGH. When DOFF pin is set LOW or

a read latency of one clock cycle.

Accesses for both ports are initiated on the rising edge of the

positive input clock (K). All synchronous input timing is refer-

enced from the rising edge of the input clocks (K and K) and all

output timing is referenced to the output clocks (C and C, or K

and K when in single clock mode).

controlled by the input clocks (K and K). All synchronous data

rising edge of the output clocks (C and C, or K and K when in

single clock mode).

through input registers controlled by the rising edge of the input

clocks (K and K).

CY7C1512KV18 is described in the following sections. The

same basic descriptions apply to CY7C1525KV18, and

CY7C1514KV18.

Read Operations

The CY7C1512KV18 is organized internally as two arrays of

2 M × 18. Accesses are completed in a burst of two sequential

18-bit data words. Read operations are initiated by asserting

RPS active at the rising edge of the positive input clock (K). The

address is latched on the rising edge of the K clock. The address

presented to the address inputs is stored in the read address

register. Following the next K clock rise, the corresponding

C as the output timing reference. On the subsequent rising edge

requested data is valid 0.45 ns from the rising edge of the output

clock (C and C or K and K when in single clock mode).

Synchronous internal circuitry automatically tristates the outputs

following the next rising edge of the output clocks (C/C). This

enables for a seamless transition between devices without the

insertion of wait states in a depth expanded memory.

ZQ

Input

Output impedance matching input. This input is used to tune the device outputs to the system data

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

PLL turn off

 Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing

in the operation with the PLL turned off differs from those listed in this data sheet. For normal operation,

connect this pin to a pull up through a 10 k

 or less pull up resistor. The device behaves in QDR I mode

when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz

with QDR I timing.

TDO

Output

Test data out (TDO) pin for JTAG.

TCK

Input

Test clock (TCK) pin for JTAG.

TDI

Input

Test data in (TDI) pin for JTAG.

TMS

Input

Test mode select (TMS) pin for JTAG.

NC

N/A

Not connected to the die. Can be tied to any voltage level.

NC/144M

Input

Not connected to the die. Can be tied to any voltage level.

NC/288M

Input

Not connected to the die. Can be tied to any voltage level.

Input-

Reference

Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC

measurement points.

Power Supply Power supply inputs to the core of the device.

Ground

Ground for the device.

Power Supply Power supply inputs for the outputs of the device.

Pin Name

I/O

Pin Description