CY7C09269V/79V/89V

CY7C09369V/89V

Document Number: 38-06056 Rev. *I

Page 9 of 22

Switching Characteristics

Over the Operating Range

Parameter

Description

CY7C09269V/79V/89V

CY7C09369V/89V

Unit

-7 [18]

-9

-12

Min

Max

Min

Max

Min

Max

–

45

–

40

–

33

MHz

–83

–

67–50

MHz

Clock Cycle Time - Flow Through

22

–

25

–

30

–

ns

Clock Cycle Time - Pipelined

12–15–20–

ns

Clock HIGH Time - Flow Through

7.5

–

12

–

12

–

ns

Clock LOW Time - Flow Through

7.5

–

12

–

12

–

ns

Clock HIGH Time - Pipelined

5–6

–8–

ns

Clock LOW Time - Pipelined

5–6

–8–

ns

Clock Rise Time

–3–

3–3

ns

Clock Fall Time

–3–

3–3

ns

Address Set-Up Time

4–4

–4–

ns

Address Hold Time

0–1

–1–

ns

Chip Enable Setup Time

4

–

4

–

4

–

ns

Chip Enable Hold Time

0

–

1

–

1

–

ns

R/W Set-Up Time

4–4

–4–

ns

R/W Hold Time

0–1

–1–

ns

Input Data Setup Time

4–4

–4–

ns

Input Data Hold Time

0–1

–1–

ns

ADS Set-Up Time

4–4

–4–

ns

ADS Hold Time

0–1

–1–

ns

CNTEN Setup Time

4.5

–

5

–

5

–

ns

CNTEN Hold Time

0–1

–1–

ns

CNTRST Setup Time

4–4

–4–

ns

CNTRST Hold Time

0–1

–1–

ns

Output Enable to Data Valid

–9–

10

–

12

ns

[19, 20]

OE to Low Z

2–2

–2–

ns

[19, 20]

OE to High Z

171

717

ns

Clock to Data Valid - Flow Through

–

18

–

20

–

25

ns

Clock to Data Valid - Pipelined

–

7.5

–

9

–

12

ns

Data Output Hold After Clock HIGH

2

–

2

–

2

–

ns

[19, 20]

Clock HIGH to Output High Z

2

9

2

9

2

9

ns

[19, 20]

Clock HIGH to Output Low Z

2

–

2

–

2

–

ns

Port to Port Delays

Write Port Clock HIGH to Read Data Delay

–

35

–

40

–

40

ns

Clock to Clock Setup Time

–

10

–

15

–

15

ns

Notes

18. See Figure 4 on page 8 for Load Conditions.

19. Test conditions used are Load 2.

20. This parameter is guaranteed by design, but it is not production tested.