CY7C2565XV18-633BZXC datasheet(1/29 Pages) CYPRESS

Part #	CY7C2565XV18-633BZXC

Description	72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Download	29 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

Logo

1 / 29 page

CY7C2563XV18, CY7C2565XV18

72-Mbit QDR® II+ Xtreme SRAM Four-Word

Burst Architecture (2.5 Cycle Read Latency) with ODT

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

, CA 95134-1709

•

408-943-2600

Document Number: 001-68997 Rev. *B

Revised June 20, 2012

72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 633 MHz clock for high bandwidth

■ Four-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces on both read and write ports

(data transferred at 1266 MHz) at 633 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-die termination (ODT) feature

❐ Supported for D[x:0], BWS[x:0], and K/K inputs

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR

® II+ Xtreme operates with 2.5 cycle read latency when

DOFF is asserted HIGH

■ Operates similar to QDR I device with 1 cycle read latency when

DOFF is asserted LOW

■ Available in × 18, and × 36 configurations

■ Full data coherency, providing most current data

■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to 1.6 V

❐ Supports 1.5 V I/O supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase-locked loop (PLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.5 cycles

CY7C2563XV18 – 4 M × 18

CY7C2565XV18 – 2 M × 36

Functional Description

The

CY7C2563XV18

and

CY7C2565XV18

are

1.8 V

Synchronous Pipelined SRAMs, equipped with QDR II+

architecture. Similar to QDR II architecture, QDR II+ architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has dedicated data

outputs to support read operations and the write port has

dedicated data inputs to support write operations. QDR II+

architecture has separate data inputs and data outputs to

completely eliminate the need to “turn-around” the data bus that

exists with common I/O devices. Each port is accessed through

a common address bus. Addresses for read and write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR II+ Xtreme read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 18-bit

words (CY7C2563XV18), or 36-bit words (CY7C2565XV18) that

burst sequentially into or out of the device. Because data is

transferred into and out of the device on every rising edge of both

input clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus “turn-arounds”.

These devices have an on-die termination feature supported for

D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external

termination resistors, reduce cost, reduce board area, and

simplify board routing.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description

633 MHz

600 MHz

Unit

Maximum Operating Frequency

633

600

MHz

Maximum Operating Current

× 18

1165

1100

mA

× 36

1660

1570

Similar Part No. - CY7C2565XV18-633BZXC

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C25652KV18	496Kb / 31P	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
	CY7C25652KV18-400BZC	496Kb / 31P	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
	CY7C25652KV18-400BZC	496Kb / 31P	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
	CY7C25652KV18-400BZI	496Kb / 31P	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
	CY7C25652KV18-400BZI	496Kb / 31P	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

More results

Similar Description - CY7C2565XV18-633BZXC

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1563XV18	1Mb / 29P	72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1563XV18	1Mb / 29P	72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C25632KV18	496Kb / 31P	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
	CY7C2562XV18	406Kb / 27P	72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
	CY7C25632KV18	496Kb / 31P	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
	CY7C2263XV18	1Mb / 29P	36-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
	CY7C1562XV18	869Kb / 29P	72-Mbit QDR짰 II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C15632KV18	783Kb / 30P	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C15632KV18	760Kb / 30P	72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1263XV18	1Mb / 30P	36-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

More results

CY7C2565XV18-633BZXC Datasheet(PDF) 1 Page - Cypress Semiconductor

CY7C2565XV18-633BZXC Datasheet(HTML) 1 Page - Cypress Semiconductor

Similar Part No. - CY7C2565XV18-633BZXC

Similar Description - CY7C2565XV18-633BZXC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL