CY7C09159AV

Document Number: 38-06053 Rev. *E

Page 2 of 19

Functional Description

The CY7C09159AV is a high-speed synchronous CMOS 8 K × 9

dual-port static RAM. Two ports are provided, permitting

independent, simultaneous access for reads and writes to any

location in memory.[1] Registers on control, address, and data

lines allow for minimal setup and hold times. In pipelined output

mode, data is registered for decreased cycle time. Clock to data

used to bypass the pipelined output register to eliminate access

after the address is clocked into the device. Pipelined output or

flow-through mode is selected via the FT/Pipe pin.

Each port contains a burst counter on the input address register.

The internal write pulse width is independent of the

LOW- to-HIGH transition of the clock signal. The internal write

pulse is self-timed to allow the shortest possible cycle times.

down the internal circuitry to reduce the static power

consumption. The use of multiple Chip Enables allows easier

banking of multiple chips for depth expansion configurations. In

HIGH to reactivate the outputs.

Counter enable inputs are provided to stall the operation of the

address input and utilize the internal address generated by the

internal counter for fast interleaved memory applications. A

port’s burst counter is loaded with the port’s Address Strobe

(ADS). When the port’s Count Enable (CNTEN) is asserted, the

address counter will increment on each LOW-to-HIGH transition

of that port’s clock signal. This will read/write one word from/into

each successive address location until CNTEN is deasserted.

The counter can address the entire memory array and will loop

back to the start. Counter Reset (CNTRST) is used to reset the

burst counter.

All parts are available in 100-pin thin quad plastic flatpack

(TQFP) packages.

Note

1. When simultaneously writing to the same location, final value cannot be guaranteed.