CY7C1525KV18

CY7C1512KV18

CY7C1514KV18

Document Number: 001-00436 Rev. *P

Page 7 of 34

Pin Definitions

Pin Name

I/O

Pin Description

Input-

Synchronous

Data input signals. Sampled on the rising edge of K and K clocks during valid write operations.

CY7C1525KV18

CY7C1512KV18

CY7C1514KV18

WPS

Input-

Synchronous

Write Port Select

 Active LOW. Sampled on the rising edge of the K clock. When asserted active, a

Input-

Synchronous

Byte Write Select 0, 1, 2, and 3

 Active LOW. Sampled on the rising edge of the K and K clocks during

write operations. Used to select which byte is written into the device during the current portion of the

write operations. Bytes not written remain unaltered.

CY7C1525KV18

CY7C1512KV18

CY7C1514KV18

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device.

A

Input-

Synchronous

Address inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during

active read and write operations. These address inputs are multiplexed for both read and write

operations. Internally, the device is organized as 8 M × 9 (2 arrays each of 4 M × 9) for CY7C1525KV18,

4 M × 18 (2 arrays each of 2 M × 18) for CY7C1512KV18, and 2 M × 36 (2 arrays each of 1 M × 36) for

CY7C1514KV18. Therefore, only 22 address inputs are needed to access the entire memory array of

CY7C1525KV18, 21 address inputs for CY7C1512KV18, and 20 address inputs for CY7C1514KV18.

These inputs are ignored when the appropriate port is deselected.

Output-

Synchronous

Data output signals. These pins drive out the requested data during a read operation. Valid data is

driven out on the rising edge of the C and C clocks during read operations, or K and K when in single

CY7C1525KV18

CY7C1512KV18

CY7C1514KV18

RPS

Input-

Synchronous

Read Port Select

 Active LOW. Sampled on the rising edge of positive input clock (K). When active,

a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access

is allowed to complete and the output drivers are automatically tristated following the next rising edge of

the C clock. Each read access consists of a burst of two sequential transfers.

C

Input Clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from

the device. Use C and C together to deskew the flight times of various devices on the board back to the

controller. See Application Example on page 10 for further details.

C

Input Clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from

the device. Use C and C together to deskew the flight times of various devices on the board back to the

controller. See Application Example on page 10 for further details.

K

Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device

edge of K.

K

Input Clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and

CQ

Echo Clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing

for the echo clocks is shown in Switching Characteristics on page 25.

CQ

Echo Clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing

for the echo clocks is shown in the Switching Characteristics on page 25.