CY7C2563XV18-633BZC datasheet(8/29 Pages) CYPRESS

Part #	CY7C2563XV18-633BZC

Description	72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C2563XV18, CY7C2565XV18

Document Number: 001-68997 Rev. *B

Page 8 of 29

select input can deselect the specified port. Deselecting a port

does not affect the other port. All pending transactions (read and

write) are completed before the device is deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin

on the SRAM and VSS to allow the SRAM to adjust its output

driver impedance. The value of RQ must be 5 × the value of the

intended line impedance driven by the SRAM, the allowable

range of RQ to guarantee impedance matching with a tolerance

of ±15% is between 175

 and 350 , with V

DDQ =1.5 V. The

output impedance is adjusted every 1024 cycles upon power up

to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the QDR II+ Xtreme to simplify data

capture on high-speed systems. Two echo clocks are generated

by the QDR II+ Xtreme. CQ is referenced with respect to K and

CQ is referenced with respect to K. These are free-running

clocks and are synchronized to the input clock of the QDR II+

Xtreme. The timing for the echo clocks is shown in the Switching

Characteristics on page 23.

Valid Data Indicator (QVLD)

QVLD is provided on the QDR II+ Xtreme to simplify data capture

on high speed systems. The QVLD is generated by the QDR II+

Xtreme device along with data output. This signal is also

edge-aligned with the echo clock and follows the timing of any

data pin. This signal is asserted half a cycle before valid data

arrives.

On-Die Termination (ODT)

These devices have an on-die termination feature for Data inputs

(D[x:0]), Byte Write Selects (BWS[x:0]), and Input Clocks (K and

K). The termination resistors are integrated within the chip. The

ODT range selection is enabled through ball R6 (ODT pin). The

ODT termination tracks value of RQ where RQ is the resistor tied

to the ZQ pin. ODT range selection is made during power up

initialization. A LOW on this pin selects a low range that follows

RQ/3.33 for 175

< RQ < 350 (where RQ is the resistor tied

to ZQ pin)

A HIGH on this pin selects a high range that follows

RQ/1.66 for 175

< RQ < 250 (where RQ is the resistor tied

to ZQ pin). When left floating, a high range termination value is

selected by default. For a detailed description on the ODT

implementation, see the application note, On-Die Termination for

QDRII+/DDRII+ SRAMs.

PLL

These chips use a PLL that is designed to function between

120 MHz and the specified maximum clock frequency. During

power up, when the DOFF is tied HIGH, the PLL is locked after

100

s of stable clock. The PLL can also be reset by slowing or

stopping the input clocks K and K for a minimum of 30 ns.

However, it is not necessary to reset the PLL to lock to the

desired frequency. The PLL automatically locks 100

s after a

stable clock is presented. The PLL may be disabled by applying

ground to the DOFF pin. When the PLL is turned off, the device

behaves in QDR I mode (with one cycle latency and a longer

access time). For information, see the application note, PLL

Considerations in QDRII/DDRII/QDRII+/DDRII+ SRAMs.

Application Example

Figure 2 shows two QDR II+ Xtreme used in an application.

Figure 2. Application Example

BUS MASTER

(CPU or ASIC)

DATA IN

DATA OUT

Address

Source K

Vt

R

D

A

K

SRAM #2

RQ = 250 ohms

ZQ

CQ/CQ

Q

K

RPS WPS BWS

D

A

K

SRAM #1

RQ = 250 ohms

ZQ

CQ/CQ

Q

K

RPS WPS BWS

RPS

WPS

BWS

CLKIN1/CLKIN1

R = 50ohms, Vt = V

/2

DDQ

R

ODT

R

CLKIN2/CLKIN2

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