CY7C1470V25

CY7C1472V25

CY7C1474V25

Document Number: 38-05290 Rev. *O

Page 9 of 38

Pin Definitions

Pin Name

I/O Type

Pin Description

Input-

synchronous

Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK.

Input-

synchronous

Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on

WE

Input-

synchronous

Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal

must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

synchronous

Advance/load input used to advance the on-chip address counter or load a new address. When

HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address

can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in

order to load a new address.

CLK

Input-

clock

Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is

only recognized if CEN is active LOW.

Input-

synchronous

Input-

synchronous

Input-

synchronous

OE

Input-

asynchronous

Output enable, active LOW. Combined with the synchronous logic block inside the device to control

the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted

HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write

sequence, during the first clock when emerging from a deselected state and when the device has been

deselected.

CEN

Input-

synchronous

Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.

When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,

CEN can be used to extend the previous cycle when required.

I/O-

synchronous

Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the

during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the

are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write

sequence, during the first clock when emerging from a deselected state, and when the device is deselected,

regardless of the state of OE.

I/O-

synchronous

MODE

Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled

LOW selects the linear burst order. MODE should not change states during operation. When left floating

MODE will default HIGH, to an interleaved burst order.

TDO

JTAG serial

output

synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

TDI

JTAG serial

input

synchronous

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.