CY7C1319KV18, CY7C1321KV18

Document Number: 001-58906 Rev. *E

Page 6 of 31

Functional Overview

The CY7C1319KV18, and CY7C1321KV18 are synchronous

pipelined Burst SRAMs equipped with a DDR interface, which

operates with a read latency of one and half cycles when DOFF

pin is tied HIGH. When DOFF pin is set LOW or connected to

one clock cycle.

Accesses are initiated on the rising edge of the positive input

clock (K). All synchronous input timing is referenced from the

rising edge of the input clocks (K and K) and all output timing is

referenced to the rising edge of the output clocks (C/C, or K/K

when in single clock mode).

controlled by the rising edge of the input clocks (K and K). All

controlled by the rising edge of the output clocks (C/C, or K/K

when in single-clock mode).

input registers controlled by the rising edge of the input clock (K).

CY7C1319KV18 is described in the following sections. The

same basic descriptions apply to CY7C1321KV18.

Read Operations

The CY7C1319KV18 is organized internally as four arrays of

256 K × 18. Accesses are completed in a burst of four sequential

18-bit data words. Read operations are initiated by asserting

R/W HIGH and LD LOW at the rising edge of the positive input

clock (K). The address presented to address inputs is stored in

the read address register and the least two significant bits of the

address are presented to the burst counter. The burst counter

increments the address in a linear fashion. Following the next K

clock rise, the corresponding 18-bit word of data from this

timing reference. On the subsequent rising edge of C the next

18-bit data word from the address location generated by the

requested data is valid 0.45 ns from the rising edge of the output

clock (C or C, or K and K when in single clock mode for 250 MHz

device). To maintain the internal logic, each read access must be

allowed to complete. Each read access consists of four 18-bit

data words and takes two clock cycles to complete. Therefore,

read accesses to the device cannot be initiated on two consec-

utive K clock rises. The internal logic of the device ignores the

second read request. Read accesses can be initiated on every

other K clock rise. Doing so pipelines the data flow such that data

is transferred out of the device on every rising edge of the output

clocks (C/C or K/K when in single-clock mode).

The

CY7C1319KV18

first

completes

the

pending

read

transactions, when read access is deselected. Synchronous

internal circuitry automatically tristates the output following the

next rising edge of the positive output clock (C). This enables a

seamless transition between devices without the insertion of wait

states in a depth expanded memory.

DOFF

Input

PLL turn off

Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing

in the PLL turned off operation is different from that listed in this data sheet. For normal operation, this

pin is connected to a pull up through a 10 K ohm or less pull up resistor. The device behaves in DDR I

mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to

167 MHz with DDR I timing.

TDO

Output

TDO pin for JTAG.

TCK

Input

TCK pin for JTAG.

TDI

Input

TDI pin for JTAG.

TMS

Input

TMS pin for JTAG.

NC

N/A

Not connected to the die. Can be tied to any voltage level.

NC/36M

N/A

Not connected to the die. Can be tied to any voltage level.

NC/72M

N/A

Not connected to the die. Can be tied to any voltage level.

NC/144M

N/A

Not connected to the die. Can be tied to any voltage level.

NC/288M

N/A

Not connected to the die. Can be tied to any voltage level.

Input-

reference

Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC

measurement points.

Power supply Power supply inputs to the core of the device.

Ground

Ground for the device.

Power supply Power supply inputs for the outputs of the device.

Pin Name

I/O

Pin Description