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CY7C1347G-133AXC Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY7C1347G-133AXC Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 25 page  CY7C1347G Document Number: 38-05516 Rev. *L Page 8 of 25 to the DQs and DQPs inputs. Doing so tristates the output drivers. As a safety precaution, DQs and DQPs are automatically tristated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1347G provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user-selectable through the MODE input. Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Sequence First Address A[1:0] Second Address A[1:0] Third Address A[1:0] Fourth Address A[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Sequence First Address A[1:0] Second Address A[1:0] Third Address A[1:0] Fourth Address A[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Snooze mode standby current ZZ > VDD 0.2 V – 40 mA tZZS Device operation to ZZ ZZ > VDD 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC –ns tZZI ZZ Active to snooze current This parameter is sampled – 2tCYC ns tRZZI ZZ Inactive to exit snooze current This parameter is sampled 0 – ns |
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