CY7C0851V/CY7C0851AV

CY7C0852V/CY7C0852AV

CY7C0853V/CY7C0853AV

Document Number: 38-06070 Rev. *L

Page 8 of 39

Master Reset

The FLEx36 family devices undergo a complete reset by taking

its

MRST

input

LOW.

The

MRST

input

can

switch

asynchronously to the clocks. The MRST initializes the internal

burst counters to zero, and the counter mask registers to all ones

(completely unmasked). The MRST also forces the Mailbox

Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags

HIGH. The MRST must be performed on the FLEx36 family

devices after power up.

Mailbox Interrupts

The upper two memory locations may be used for message

passing and permit communications between ports. Table 1

shows

the

interrupt

operation

for

both

ports

of

CY7C853V/CY7C0853AV. The highest memory location, 3FFFF

is the mailbox for the right port and 3FFFE is the mailbox for the

At least one byte has to be active for a Write to generate an

interrupt. A valid Read of the 3FFFF location by the right port

a Read to reset the interrupt. When one port Writes to the other

port’s mailbox, the INT of the port that the mailbox belongs to is

asserted LOW. The INT is reset when the owner (port) of the

mailbox Reads the contents of the mailbox. The interrupt flag is

set in a flow-thru mode (that is it follows the clock edge of the

writing port). Also, the flag is reset in a flow-thru mode (that is it

follows the clock edge of the reading port).

Each port can read the other port’s mailbox without resetting the

interrupt. And each port can write to its own mailbox without

setting the interrupt. If an application does not require message

passing, INT pins should be left open.

Table 1. Interrupt Operation Example [5, 6, 7, 8, 9]

Function

Left Port

Right Port

L

L

3FFFF

X

X

X

X

L

X

X

X

X

H

L

3FFFF

H

X

X

X

L

L

L

3FFFE

X

H

L

3FFFE

H

X

X

X

X

Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port) [10, 11]

CLK

MRST

CNT/MSK CNTRST

ADS

CNTEN

Operation

Description

X

L

XXXX

Master reset

Reset address counter to all 0s and mask

register to all 1s.

H

H

L

X

X

Counter reset

Reset counter unmasked portion to all 0s.

H

H

H

L

L

Counter load

Load counter with external address value

presented on address lines.

H

H

H

L

H

Counter readback

Read out counter internal value on address

lines.

HHHH

L

Counter increment Internally increment address counter value.

HHHHH

Counter hold

Constantly hold the address value for

multiple clock cycles.

H

L

L

X

X

Mask reset

Reset mask register to all 1s.

H

L

H

L

L

Mask load

Load mask register with value presented on

the address lines.

H

L

H

L

H

Mask readback

Read out mask register value on address

lines.

H

L

H

H

X

Reserved

Operation undefined

Notes

5. 9 M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits.

can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.

7. OE is “Don’t Care” for mailbox operation.

8. At least one of B0, B1, B2, or B3 must be LOW.

9. A16x is a NC for CY7C0851V/CY7C0851AV, therefore the Interrupt Addresses are FFFF and EFFF.

10. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.

11. Counter operation and mask register operation is independent of chip enables.