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CY7C0832AV-133AXI Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY7C0832AV-133AXI Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 31 page  CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833V Document #: 38-06059 Rev. *W Page 9 of 31 Retransmit Retransmit is a feature that allows the Read of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal mirror register is used to store the initially loaded address counter value. When the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this mirror register. If the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the mirror register. Thus, the repeated access of the same data is allowed without the need for any external logic. Mask Reset Operation The mask register is reset to all ‘1s,’ which unmasks every bit of the counter. Master reset (MRST) also resets the mask register to all ‘1s’. Mask Load Operation The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment operations. Permitted values are of the form 2n – 1 or 2n – 2. From the most significant bit to the least significant bit, permitted values have zero or more ‘0s,’ one or more ‘1s,’ or one ‘0.’ Thus 3FFFF, 003FE, and 00001 are permitted values, but 3F0FF, 003FC, and 00000 are not. Mask Readback Operation The internal value of the mask register can be read out on the address lines. Readback is pipelined; the address is valid tCM2 after the next rising edge of the port’s clock. If mask readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) is three-stated. Figure 3 on page 10 shows a block diagram of the operation. Counting by Two When the least significant bit of the mask register is ‘0,’ the counter increments by two. This may be used to connect the × 18 devices as a 36-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 36-bit data in even memory locations, and the other half in odd memory locations. Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port) [19, 20] CLK MRST CNT/MSK CNTRST ADS CNTEN Operation Description X L X X X X Master Reset Reset address counter to all 0s and mask register to all 1s. H H L X X Counter Reset Reset counter unmasked portion to all 0s. H H H L L Counter Load Load counter with external address value presented on address lines. H H H L H Counter Readback Read out counter internal value on address lines. H H H H L Counter Increment Internally increment address counter value. H H H H H Counter Hold Constantly hold the address value for multiple clock cycles. H L L X X Mask Reset Reset mask register to all 1s. H L H L L Mask Load Load mask register with value presented on the address lines. H L H L H Mask Readback Read out mask register value on address lines. H L H H X Reserved Operation undefined Notes 19. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW. 20. Counter operation and mask register operation is independent of chip enables. |
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