CY7C006AV-25AXC datasheet(7/21 Pages) CYPRESS

Part #	CY7C006AV-25AXC

Description	3.3 V 8 K / 16 K 횞 8 Asynchronous Dual-Port Static RAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C144AV

CY7C006AV

Document Number: 38-06051 Rev. *H

Page 7 of 21

Data Retention Mode

The CY7C144AV and CY7C006AV are designed with battery

backup in mind. Data retention voltage and supply current are

guaranteed over temperature. The following rules ensure data

retention:

1. Chip enable (CE) must be held HIGH during data retention,

within VCC to VCC – 0.2 V.

2. CE must be kept between VCC – 0.2 V and 70% of VCC during

the power-up and power-down transitions.

3. The RAM can begin operation > tRC after VCC reaches the

minimum operating voltage (3.0 Volts).

AC Test Loads and Waveforms

Figure 3. AC Test Loads and Waveforms

3.0V

GND

90%

10%

3ns

3 ns

10%

ALL INPUT PULSES

(a) Normal Load (Load 1)

R1 = 590



3.3 V

OUTPUT

R2 = 435



C= 30 pF

VTH =1.4 V

OUTPUT

C = 30 pF

(b) Thévenin Equivalent (Load 1)

(c) Three-State Delay(Load 2)

R1 = 590



R2 = 435



3.3 V

OUTPUT

C= 5pF

RTH = 250 



including scope and jig)

(Used for tLZ, tHZ, tHZWE & tLZWE

Timing

Figure 4. Timing

Parameter

Test Conditions [8]

Max

Unit

ICCDR1

@ VCCDR = 2 V

50

A

Data Retention Mode

3.0 V

VCC 2.0 V

VCC to VCC – 0.2 V

VCC

CE

tRC

V

IH

Note

8. CE = VCC, VIN = GND to VCC, TA = 25 °C. This parameter is guaranteed but not tested.

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