CY7C008V/009V

CY7C018V/019V

Document Number: 38-06044 Rev. *E

Page 3 of 23

Contents

Pin Configurations ........................................................... 4

Selection Guide ................................................................ 5

Pin Definitions .................................................................. 6

Maximum Ratings ............................................................. 6

Operating Range ............................................................... 6

Electrical Characteristics ................................................. 7

Capacitance ...................................................................... 7

AC Test Loads and Waveforms ....................................... 8

Switching Characteristics ................................................ 8

Data Retention Mode ...................................................... 10

Timing .............................................................................. 10

Switching Waveforms .................................................... 11

Read Cycle No.1 (Either Port Address Access) ........ 11

Read Cycle No.2 (Either Port CE/OE Access) .......... 11

Read Cycle No. 3 (Either Port) .................................. 11

Write Cycle No. 1: R/W Controlled Timing ................ 12

Write Cycle No. 2: CE Controlled Timing .................. 12

Semaphore Read After Write Timing, Either Side ..... 13

Timing Diagram of Semaphore Contention ............... 13

Timing Diagram of Read with BUSY (M/S=HIGH) .... 14

Write Timing with Busy Input (M/S=LOW) ................. 14

Busy Timing Diagram No. 1 (CE Arbitration) ............. 15

Busy Timing Diagram No. 2 (Address Arbitration) .... 15

Architecture .................................................................... 17

Functional Description ................................................... 17

Write Operation ......................................................... 17

Read Operation ......................................................... 17

Interrupts ................................................................... 17

Busy .......................................................................... 17

Master/Slave ............................................................. 17

Semaphore Operation ............................................... 17

Ordering Information ...................................................... 19

128 K × 8 3.3 V Asynchronous Dual-Port SRAM ...... 19

Ordering Code Definitions ......................................... 19

Package Diagram ............................................................ 20

Acronyms ........................................................................ 21

Document Conventions ................................................. 21

Units of Measure ....................................................... 21

Document History Page ................................................. 22

Sales, Solutions, and Legal Information ...................... 23

Worldwide Sales and Design Support ....................... 23

Products .................................................................... 23

PSoC Solutions ......................................................... 23

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