CY7C130, CY7C130A

CY7C131, CY7C131A

Document Number: 38-06002 Rev. *H

Page 10 of 22

Busy/Interrupt Timing

BUSY LOW from address match

–

20

–

25

–

30

ns

BUSY HIGH from address mismatch[30]

–

20

–

25–30

ns

BUSY LOW from CE LOW

–

20

–

25

–

30

ns

BUSY HIGH from CE HIGH[30]

–

20

–

25–30

ns

Port set-up for priority

5

–

5

–

5

–

ns

[31]

R/W LOW after BUSY LOW

0

–

0

–

0

–

ns

R/W HIGH after BUSY HIGH

30

–

35

–

35

–

ns

BUSY HIGH to valid data

–

35

–

45

–

45

ns

Write data valid to read data valid

–

Note 32

–

Note 32

–

Note 32

ns

Write pulse to data delay

–

Note 32

–

Note 32

–

Note 32

ns

Interrupt Timing

R/W to INTERRUPT set time

–

25

–

35

–

45

ns

CE to INTERRUPT set time

–

25

–

35

–

45

ns

Address to INTERRUPT set time

–

25

–

35

–

45

ns

OE to INTERRUPT reset time[20]

–

25

–

35–45

ns

CE to INTERRUPT reset time[20]

–

25

–

35–45

ns

Address to INTERRUPT reset time[20]

–

25

–

35–45

ns

Switching Characteristics

Parameter

Description

7C130-35

7C131-35

7C140-35

7C141-35

7C130-45

7C131-45

7C140-45

7C141-45

7C130-55

7C131-55

7C140-55

7C141-55

Unit

Min

Max

Min

Max

Min

Max

Notes

30. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.

31. CY7C140/CY7C141 only.

32. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:

BUSY on Port B goes HIGH.

Port B’s address is toggled.

CE for Port B is toggled.

R/W for Port B is toggled during valid read.