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CY7C027V-25AC Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY7C027V-25AC Datasheet(HTML) 5 Page - Cypress Semiconductor |
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5 / 22 page  CY7C027V/027AV/028V CY7C037AV/038V Document #: 38-06078 Rev. *E Page 5 of 22 Architecture The CY7C027V/027AV/028V and CY7037AV/038V consist of an array of 32K and 64K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. Functional Description The CY7C027V/027AV/028V and CY7037AV/038V are low power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as stand-alone 16/18-bit dual-port static RAMs or multiple devices can be combined to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a chip select (CE) pin. The CY7C027V/027AV/028V and CY7037AV/038V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP). Write Operation Data must be set up for a duration of tSD before the rising edge of R/W to guarantee a valid write. A write operation is controlled by either the R/W pin (see Figure 7) or the CE pin (see Figure 8). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (7FFF for the CY7C027V/037AV/027AV, FFFF for the CY7C028V/38V) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027V/027AV/037AV, FFFE for the CY7C028V/38V) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Pin Definitions Left Port Right Port Description CE0L, CE1L CE0R, CE1R Chip Enable (CE is LOW when CE0 VIL and CE1 VIH) R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A15L A0R–A15R Address (A0–A14 for 32K; A0–A15 for 64K devices) I/O0L–I/O17L I/O0R–I/O17R Data bus input/output (I/O0–I/O15 for x16 devices; I/O0–I/O17 for x18) SEML SEMR Semaphore Enable UBL UBR Upper byte select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices) LBL LBR Lower byte select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices) INTL INTR Interrupt flag BUSYL BUSYR Busy flag M/S Master or Slave select VCC Power GND Ground NC No connect |
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