CY2DP818ZXC datasheet(7/13 Pages) CYPRESS

Part #	CY2DP818ZXC

Description	1:8 Clock Fanout Buffer

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY2DP818

Document Number: 38-07061 Rev. *D

Page 7 of 13

AC Switching Characteristics

Table 7. LVPECL Output, VDD = 3.3 V ± 5%, TA = 0 C to 70C or –40 C to 85 C

Parameter

Description

Conditions

Min

Typ

Max

Unit

VOD

Driver Differential Output voltage

p-p

VDD = Min, VIN = VIH or VIL,

RL = 50 

1000

–

3600

mV

VOC

Driver common-mode p-p

VDD = Min, VIN = VIH or VIL,

RL = 50 

––

300

mV

tR

Rise Time

Differential 20% to 80%,

CL = 10 pF to GND,

RL = 50  to GND

300

–

1200

ps

tF

Fall Time

VOH

Output High Voltage

VDD = Min, VIN = VIH or VIL,

IOH = –12 mA

2.1

–

3.0

V

VOL[2]

Output Low Voltage

VDD = Min, VIN = VIH or VIL

0.8

–

1.3

V

IOS

Short Circuit Current

VDD = Max, VOUT = GND

–125

–

–150

mA

Table 8. VDD = 3.3 V ± 5%, TA = 0 C to 70 C or –40 C to 85 C

Parameter

Description

Conditions

Min

Typ

Max

Unit

tPLH

Propagation Delay – Low to High VID = 100 mV

3

4

5

ns

tPHL

Propagation Delay – High to Low VID = 100 mV

3

4

5

ns

tSK(0)

Output Skew: Skew between

outputs of the same package

(in phase)

–

0.2

ns

tSK(p)

Pulse Skew: Skew between

opposite transitions of the same

output (tPHL–tPLH)

–

0.2

–

ns

tSK(t)

Package Skew: Skew between

outputs of different packages at

the same power supply voltage,

temperature and package type.

Same input signal level and

output load.

VID = 100 mV

–

1

ns

Table 9. High frequency Parametrics

Parameter

Description

Conditions

Min

Typ

Max

Unit

Fmax

Maximum frequency

VDD = 3.3 V

45%–55% duty cycle

Standard load circuit

–

350

MHz

Note

2. VOL levels are dependent on the termination voltage VTT and termination resistance RTT. Changing either of these values will affect VOL.

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