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SL1062A Datasheet(PDF) 4 Page - System Logic Semiconductor

Part No. SL1062A
Description  Low Voltage Transmission Circuit with Dialler Interface
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Maker  SLS [System Logic Semiconductor]
Homepage  http://www.slsemicon.co.kr/e_index.htm
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SL1062A Datasheet(HTML) 4 Page - System Logic Semiconductor

   
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SL1062A
System Logic
Semiconductor
SLS
Automatic gain control input AGC
Automatic line loss compensation is achieved by
connecting a resistor (R6) between AGC and VEE.
The automatic gain control varies the gain of the
microphone amplifier and the receiving amplifier in
accordance with the DC line current. The control
range is 5.8 dB which corresponds to a line length of
5 km for a 0.5 mm diameter twisted-pair copper cable
with a DC resistance of 176
Ω/km and average
attenuation of 1.2 dB/km. Resistor R6 should be
chosen in accordance with the exchange supply
voltage and its feeding bridge resistance (see
Table 1).
Table 1 Values of resistor R6 for optimum line-loss
compensation at various values of exchange supply
voltage
(Vexch)
and
exchange
feeding
bridge
resistance (Rexch); R9 = 20
Ω.
Vexch(V)
400
Rexch(
Ω)
600
Rexch(
Ω)
800
Rexch(
Ω)
1000
Rexch(
Ω)
R6(K
Ω)
36
100
78.7
-
-
48
140
110
93.1
82
60
-
-
120
102
The ratio of start and stop currents of the AGS curve
is independent of the value of R6. If no automatic
line-loss compensation is required the AGS pin may
be left open-circuit. The amplifiers, in this condition,
will give their maximum specified gain.
Sidetone suppression
The anti-sidetone network, R1//Zline, R2, R3, R8,
R9 and Zbal (see Fig4) suppresses the transmitted
signal in the earpiece. Maximum compensation is
obtained when the following conditions are fulfilled:
R9 x R2 = R1 x
( R3+
) (1)
=
(2)
It fixed values are chosen for R1, R2, R3 and R9, then
condition
(1)
will
always
be
fulfilled
when
R8//Z
bal
<<R3.
To obtain optimum sidetone suppression, condition
(2) has to be fulfilled which results in:
Zbal =
x Zline = k x Zline
Where k is a scale factor; k =
The scale factor k, dependent on the value of R8, is
chosen to meet the following criteria:
• compatibility with a standard capacitor from the
E6 or E12 range for Zbal
• Z
bal // R8
<<R3 fulfilling condition (a) and thus
ensuring correct anti-sidetone bridge operation
• Z
bal + R8
>>R9 to avoid influencing the transmit
gain.
In practise Zline varies considerably with the line type
and length. The value chosen for Zbal should
therefore be for an average line length thus giving
optimum setting for short or long lines.
MAXIMUM RATINGS
*
Symbol
Parameter
Condition
Min
Max
Unit
VLN
Positive continuous line voltage
-
12
V
VLN(R)
Repetitive line voltage during
switch-on or line interruption
-
13.2
V
VLN(RM)
Repetitive peak line voltage for a
1 ms pulse per 5 s
R9 = 20
Ω; R10 = 13 Ω;
see Fig.5
-
28
V
Iline
Line current
R9 = 20
-
140
mA
VIN
positive input voltage
-
VCC+0.7
V
negative input voltage
-
-0.7
V
PD
Total power dissipation
R9 = 20
Ω; note 1
-
666
mW
Tstg
Storage temperature
-40
+125
°C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Note 1. Calculated for the maximum operating temperature specified (Tamb = 75
°C) and a maximum junction
temperature of 125
°C.
R8 x Zbal
R8 +Zbal
R8
R1
Zbal
Zbal + R8
R8
R1
Zline
Zline + R1
Input voltage on all other pins


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