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SPC5643LF2MLQ8 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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SPC5643LF2MLQ8 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 136 page  MPC5643L Microcontroller Data Sheet, Rev. 8.1 Introduction Freescale Semiconductor 10 • Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of platforms and frequencies. • Support of address-based read access timing for emulation of other memory types. • Support for reporting of single- and multi-bit error events. • Typical operating configuration loaded into programming model by system reset. The platform flash controller is replicated for each processor. 1.5.8 Platform Static RAM Controller (SRAMC) The SRAMC module is the platform SRAM array controller, with integrated error detection and correction. The main features of the SRAMC provide connectivity for the following interfaces: • XBAR Slave Port (64-bit data path) • ECSM (ECC Error Reporting, error injection and configuration) • SRAM array The following functions are implemented: • ECC encoding (32-bit boundary for data and complete address bus) • ECC decoding (32-bit boundary and entire address) • Address translation from the AHB protocol on the XBAR to the SRAM array The platform SRAM controller is replicated for each processor. 1.5.9 Memory subsystem access time Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the slave being accessed is not parked on the requesting master in the crossbar. Table 2 shows the number of additional data phase wait states required for a range of memory accesses. Table 2. Platform memory access time summary AHB transfer Data phase wait states Description e200z4d instruction fetch 0 Flash memory prefetch buffer hit (page hit) e200z4d instruction fetch 3 Flash memory prefetch buffer miss (based on 4-cycle random flash array access time) e200z4d data read 0–1 SRAM read e200z4d data write 0 SRAM 32-bit write e200z4d data write 0 SRAM 64-bit write (executed as 2 x 32-bit writes) e200z4d data write 0–2 SRAM 8-,16-bit write (Read-modify-Write for ECC) e200z4d flash memory read 0 Flash memory prefetch buffer hit (page hit) e200z4d flash memory read 3 Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle of program flash memory controller arbitration) |
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