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MCIMX503CVM8B Datasheet(PDF) 72 Page - Freescale Semiconductor, Inc |
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MCIMX503CVM8B Datasheet(HTML) 72 Page - Freescale Semiconductor, Inc |
72 / 134 page i.MX50 Applications Processors for Consumer Products, Rev. 2 72 Freescale Semiconductor Electrical Characteristics NOTE The timing parameter DDR20(tDQSCK) is not strictly required by this DRAM MC design. 4.9 External Peripheral Interfaces The following sections provide information on external peripheral interfaces. 4.9.1 AUDMUX Timing Parameters The AUDMUX provides programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is hence governed by the SSI module. 4.9.2 CSPI and eCSPI Timing Parameters This section describes the timing parameters of the CSPI and eCSPI modules. The CSPI and eCSPI have separate timing parameters for master and slave modes. The nomenclature used with the CSPI/eCSPI modules and the respective routing of these signals is shown in Table 48. DDR21 DQS to DQ input skew tDQSQ — 0.65 ns DDR22 DQS to DQ input hold time tQH 0.45 tCK -0.85 —ns Table 48. CSPI Nomenclature and Routing Module I/O Access eCSPI1 GPIO, KPP, DISP0_DAT, CSI0_DAT, and EIM_D through IOMUX eCSPI2 DISP0_DAT, CSI0_DAT, and EIM through IOMUX CSPI DISP0_DAT, EIM_A/D, SD1, and SD2 through IOMUX Table 47. DDR2 Input AC Timing ID Description Symbol Min Max Unit |
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