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MCIMX503CVK8B Datasheet(PDF) 59 Page - Freescale Semiconductor, Inc |
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MCIMX503CVK8B Datasheet(HTML) 59 Page - Freescale Semiconductor, Inc |
59 / 134 page Electrical Characteristics i.MX50 Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 59 4.7 External Interface Module (EIM) The following sections provide information on the EIM. 4.7.1 General EIM Timing Figure 17, Figure 18, and Table 42 specify the timings related to the EIM module. All EIM output control signals may be asserted and de-asserted by an internal clock synchronized to the EIM_BCLK rising edge according to corresponding assertion/negation control fields. , Figure 17. EIM Outputs Timing Diagram NF23 preamble delay tPRE (PRE_DELAY+1)*tCK —ns NF24 postamble delay tPOST POST_DELAY*tCK —ns NF25 CLE and ALE setup time tCALS 0.5*tCK —ns NF26 CLE and ALE hold time tCALH 0.5*tCK —ns 1 GPMI’s sync mode output timing could be controlled by module’s internal register, say HW_GPMI_TIMING2_CE_DELAY, HW_GPMI_TIMING_PREAMBLE_DELAY, HW_GPMI_TIMING2_POST_DELAY. This AC timing depends on these registers’ setting. In the above table, we use CE_DELAY/PRE_DELAY/POST_DELAY representing these settings each. Table 41. Samsung Toggle Mode Timing Parameters1 (continued) ID Parameter Symbol Timing T = GPMI Clock Cycle Unit Min. Max. WE4 EIM_ADDR EIM_CSx EIM_RW EIM_OE EIM_BCLK EIM_EBx EIM_LBA EIM_DATA ... WE5 WE6 WE7 WE8 WE9 WE10 WE11 WE12 WE13 WE14 WE15 WE16 WE17 WE3 WE2 WE1 |
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