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MC10XS3412CHFK Datasheet(PDF) 37 Page - Freescale Semiconductor, Inc

Part No. MC10XS3412CHFK
Description  Quad High Side Switch (Dual 10 mOhm, Dual 12 mOhm)
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Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
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MC10XS3412CHFK Datasheet(HTML) 37 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
37
10XS3412
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Bits D5:D4 allow the MCU to select one of two analog
feedbacks on the CSNS output pin, as shown in Table 21.
The GCR register disables the over-voltage protection
(D0). When this bits is [0], the over-voltage is enabled (default
value).
ADDRESS 00111—CALIBRATION REGISTER
(CALR)
The CALR register allows the MCU to calibrate internal
clock, as explained in Figure 12.
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN DATA)
When the CS pin is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB- (OD15-)
first as the new message data is clocked into the SI pin. The
first sixteen bits of data clocking out of the SO, and following
a CS transition, is dependent upon the previously written SPI
word.
Any bits clocked out of the Serial Output (SO) pin after the
first 16 bits will be representative of the initial message bits
clocked into the SI pin since the CS pin first transitioned to a
logic [0]. This feature is useful for daisy-chaining devices as
well as message verification.
A valid message length is determined following a CS
transition of [0] to [1]. If there is a valid message length, the
data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
SO data will represent information ranging from fault
status to register contents, user selected by writing to the
STATR bits OD4, OD3, OD2, OD1, and OD0. The value of
the previous bits SOA4 and SOA3 will determine which
output the SO information applies to for the registers which
are output specific; viz., Fault, PWMR, CONFR0, CONFR1,
and OCR registers.
Note that the SO data will continue to reflect the
information for each output (depending on the previous
SOA4, SOA3 state) that was selected during the most recent
STATR write until changed with an updated STATR write.
The output status register correctly reflects the status of
the STATR-selected register data at the time that the CS is
pulled to a logic [0] during SPI communication, and/or for the
period of time since the last valid SPI communication, with
the following exception:
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
• The VPWR voltage is below 4.0 V, the status must be
ignored by the MCU.
SERIAL OUTPUT BIT ASSIGNMENT
The 16 bits of serial output data depend on the previous
serial input message, as explained in the following
paragraphs. Table 23, summarizes SO returned data for bits
OD15:OD0.
• Bit OD15 is the MSB; it reflects the state of the
Watchdog bit from the previously clocked-in message.
• Bits OD14:OD10 reflect the state of the bits
SOA4:SOA0 from the previously clocked in message.
• Bit OD9 is set to logic [1] in Normal mode (NM).
• The contents of bits OD8:OD0 depend on bits D4:D0
from the most recent STATR command SOA4:SOA0
as explained in the paragraphs following Table 23.
Table 20. PWM Module Selection
PWM_en (D7) CLOCK_sel (D6)
PWM module
0
X
PWM module disabled
(default)
1
0
PWM module enabled with
external clock from IN0
1
1
PWM module enabled with
internal calibrated clock
Table 21. CSNS Reporting Selection
TEMP_en
(D5)
CSNS_en
(D4)
CSNS reporting
0
0
CSNS tri-stated (default)
X
1
current recopy of selected output (D3:2]
bits)
1
0
temperature on GND flag
Table 22. Output Current Recopy Selection
CSNS1 (D3)
CSNS0 (D2)
CSNS reporting
0
0
HS0 (default)
0
1
HS1
1
0
HS2
1
1
HS3


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