Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MC10XS3412CHFK Datasheet(PDF) 33 Page - Freescale Semiconductor, Inc

Part No. MC10XS3412CHFK
Description  Quad High Side Switch (Dual 10 mOhm, Dual 12 mOhm)
Download  51 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
Logo 

MC10XS3412CHFK Datasheet(HTML) 33 Page - Freescale Semiconductor, Inc

Zoom Inzoom in Zoom Outzoom out
 33 / 51 page
background image
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
10XS3412
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
forward mode. No additional passive components are
required except on VDD current path.
GROUND DISCONNECT PROTECTION
In the event the 10XS3412 ground is disconnected from
load ground, the device protects itself and safely turns OFF
the output regardless of the state of the output at the time of
disconnection (maximum VPWR=16 V). A 10 kΩ resistor
needs to be added between the MCU and each digital input
pin in order to ensure that the device turns off in case of
ground disconnect and to prevent this pin from exceeding
maximum ratings.
LOSS OF SUPPLY LINES
Loss of VDD
If the external VDD supply is disconnected (or not within
specification: VDD<VDD(FAIL)) with VDD_FAIL_en bit is set to
logic [1]), all SPI register content is reset.
The outputs can still be driven by the direct inputs IN[0:3]
if VPWR is within specified voltage range. The 10XS3412
uses the battery input to power the output MOSFET-related
current sense circuitry and any other internal logic providing
Fail Safe device operation with no VDD supplied. In this state,
the over-temperature, over-current, severe short-circuit,
short to VPWR and OFF open-load circuitry are fully
operational with default values corresponding to all SPI bits
are set to logic [0]. No current is conducted from VPWR to
VDD.
Loss of VPWR
If the external VPWR supply is disconnected (or not within
specification), the SPI configuration, reporting, and daisy
chain features are provided for RST is set to logic [1] under
VDD in nominal conditions. The SPI pull-up and pull-down
current sources are not operational. This fault condition can
be diagnosed with UV fault in the SPI STATR_s registers.
The previous device configuration is maintained. No current
is conducted from VDD to VPWR.
Loss of VPWR and VDD
If the external VPWR and VDD supplies are disconnected
(or not within specification: (VDD and VPWR) <
VSUPPLY(POR)), all SPI register contents are reset with default
values corresponding to all SPI bits are set to logic [0] and all
latched faults are also reset.
EMC PERFORMANCES
All following tests are performed on Freescale evaluation
board in accordance with the typical application schematic.
The device is protected in case of positive and negative
transients on the VPWR line (per ISO 7637-2).
The 10XS3412 successfully meets Class 5 of the
CISPR25 emission standard, and 200 V/m or BCI 200 mA
injection level for immunity tests.
LOGIC COMMANDS AND REGISTERS
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 16-bit
messages. A message is transmitted by the MCU starting
with the MSB D15 and ending with the LSB, D0 (Table 10).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB,
D15, is the watchdog bit (WDIN). In some cases, output
selection is done with bits D14:D13. The next three bits,
D12:D10, are used to select the command register. The
remaining nine bits, D8:D0, are used to configure and control
the outputs and their protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy-chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
The 10XS3412 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 11 summarizes the SI registers.
Table 10. SI Message Bit Assignment
Bit Sig
SI Msg Bit
Message Bit Description
MSB
D15
Watchdog in: toggled to satisfy watchdog requirements.
D14
:D13
Register address bits used in some cases for output selection (
Table 12).
D12
:D10
Register address bits.
D9
Not used (set to logic [0]).
LSB
D8:D0
Used to configure the inputs, outputs, and the device protection features and SO status content.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn