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MC10XS3412CHFK Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc

Part No. MC10XS3412CHFK
Description  Quad High Side Switch (Dual 10 mOhm, Dual 12 mOhm)
Download  51 Pages
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Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
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MC10XS3412CHFK Datasheet(HTML) 29 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
29
10XS3412
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FAIL SAFE MODE
The 10XS3412 is in Fail Safe mode when:
•VPWR is within the normal voltage range,
• wake-up = 1,
• fail = 1,
•fault = 0.
Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or IN_ON[0:3] or
RST
input pin transitions from logic [0] to logic [1]. The WAKE
input is capable of being pulled up to VPWR with a series of
limiting resistance limiting the internal clamp current
according to the specification.
The watchdog timeout is a multiple of an internal oscillator.
As long as the WD bit (D15) of an incoming SPI message is
toggled within the minimum watchdog timeout period
(WDTO), the device will operate normally.
Fail Safe conditions
If an internal watchdog timeout occurs before the WD bit
for FSI open (Table 9) or in case of VDD failure condition
(VDD< VDD(FAIL))) for VDD_FAIL_en bit is set to logic [1], the
device will revert to a Fail Safe mode until the WD bit is
written to logic [1] (see Fail Safe to Normal mode transition
paragraph) and VDD is within the normal voltage range.
During the Fail Safe mode, the outputs will depend on the
corresponding input. The SPI register content is reset to their
default value (except POR bit) and fault protections are fully
operational.
The Fail Safe mode can be detected by monitoring the NM
bit is set to [0].
NORMAL & FAIL SAFE MODE TRANSITIONS
Transition Fail Safe to Normal mode
To leave the Fail Safe mode, VDD must be in nominal
voltage and the microcontroller has to send a SPI command
with WDIN bit set to logic [1] ; the other bits are not
considered. The previous latched faults are reset by the
transition into Normal mode (autoretry included).
Moreover, the device can be brought out of the Fail Safe
mode due to watchdog timeout issue by forcing the FSI pin to
logic [0].
Transition Normal to Fail-Safe mode
To leave the Normal mode, a Fail-safe condition must
occurred (fail=1). The previous latched faults are reset by the
transition into Fail-safe mode (autoretry included).
FAULT MODE
The 10XS3412 is in Fault mode when:
•VPWR and VDD are within the normal voltage range
• wake-up = 1
• fail = X
• fault=1
This device indicates the faults below as they occur by
driving the FS pin to logic [0] for RST input is pulled up:
• Over-temperature fault
• Over-current fault
• Severe short-circuit fault
• Output(s) shorted to VPWR fault in OFF state
• Open load fault in OFF state
• Over-voltage fault (enabled by default)
• Under-voltage fault
The FS pin will automatically return to logic [1] when the
fault condition is removed, except for over-current, severe
short-circuit, over-temperature and under-voltage which will
be reset by a new turn-on command (each fault_control
signal to be toggled).
Fault information is retained in the SPI fault register and is
available (and reset) via the SO pin during the first valid SPI
communication.
The Open load fault in ON state is only reported through
SPI register without effect on the corresponding output state
(HS[x]) and the FS pin.
START-UP SEQUENCE
The 10XS3412 enters in Normal mode after start-up if
following sequence is provided:
• VPWR and VDD power supplies must be above their
under-voltage thresholds,
• generate wake-up event (wake-up=1) from 0 to 1 on
RST. The device switches to Normal mode with SPI
register content is reset (as defined in Table 11 and
Table 23). All features of the 10XS3412 will be available
after 50
μs typical and all SPI registers are set to default
values (set to logic [0]). The UV fault is reported in the
SPI status registers.
And, in case of the PWM module is used (PWM_en bit is
set to logic [1]) with an external reference clock:
• apply PWM clock on IN0 input pin after maximum
200
μs (min. 50 μs).
If the correct start-up sequence is not provided, the PWM
function is not guaranteed.
Table 9. SPI Watchdog Activation
Typical RFSI (
Ω)
Watchdog
0 (shorted to ground)
Disabled
(open)
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