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MCIMX508CVM8B Datasheet(PDF) 100 Page - Freescale Semiconductor, Inc |
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MCIMX508CVM8B Datasheet(HTML) 100 Page - Freescale Semiconductor, Inc |
100 / 134 page i.MX50 Applications Processors for Consumer Products, Rev. 2 100 Freescale Semiconductor Package Information and Contact Assignments 4.9.11.4 USB VBUS Parameters Table 77 lists the USB VBUS input parameters. 5 Package Information and Contact Assignments This section includes the contact assignment information and mechanical package drawing. 5.1 13 x 13 mm, 0.5 mm Pitch, 416 Pin MAPBGA Package Information This section contains the outline drawing, signal assignment map, ground, power, reference ID (by ball grid location) for the 13 x 13 mm, 0.5 mm pitch, 416 pin MAPBGA package. Jitter (peak-peak) <1.2 MHz 0 — 50 ps Jitter (peak-peak) >1.2 MHz 0 — 100 ps Duty-cycle Reference Clock frequency 24 MHz 40 — 60 % Table 77. VBUS Comparators Thresholds Parameter Conditions Min Typ Max Unit A-Device Session Valid Comparator Threshold — 0.8 1.4 2.0 V B-Device Session Valid Comparator Threshold — 0.8 1.4 4.0 V B-Device Session End Comparator Threshold — 0.2 0.45 0.8 V VBUS Valid Comparator Threshold1 1 For VBUS maximum rating, see Table 7. —4.4 4.6 4.75 V VBUS for CHGR_DET_B Operation — 3.0 — — V VBUS Input Current VBUS = 5.25 V — — 350 μA Table 76. USB PHY System Clocking Parameters (continued) Parameter Conditions Min Typ Max Unit |
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